24C04-24C04. Fast Delivery |IC PHOENIX CO.,LIMITED

24C04. ,4KbitSerialI2CBusEEPROMwithUser-DefinedBlockWriteProtectionLogic DiagramSELF TIMED PROGRAMMING CYCLEAUTOMATIC ADDRESS INCREMENTINGENHANCED ESD/LATCH UPPERFORM ..
24C04A , The FT24C04A/08A/16A series are 4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 512/1024/2048 words of 8 bits (1 byte) each.
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24C08 ,8K/16K5.0VI2COSerialEEPROMsST24C08, ST25C08 ST24W08, ST25W0828 Kbit Serial I C Bus EEPROMwith User-Defined Block Write Protect ..
24C08A ,2-Wire Serial EEPROMFeatures• Write Protect Pin for Hardware Data Protection – Utilizes Different Array Protection Comp ..
24C08N ,Two-wore Serial EEPROMFeatures• Low-voltage and Standard-voltage Operation– 2.7 (V = 2.7V to 5.5V)CC– 1.8 (V = 1.8V to 5. ..
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2N4427 ,Leaded Small Signal Transistor General Purpose

24C04-24C04.
4KbitSerialI2CBusEEPROMwithUser-DefinedBlockWriteProtection
ST24C04, ST25C04
ST24W04, ST25W04
4 Kbit Serial I2 C Bus EEPROM
with User-Defined Block Write Protection
February 1999 1/16
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE: 3V to 5.5V for ST24x04 versions 2.5V to 5.5V for ST25x04 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W04 and ST25W04
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 4 Kbits I2 C bus
EEPROM products, the ST24/25C04 and the
ST24/25W04. In the text, products are referred to
as ST24/25x04, where "x" is: "C" for Standard
version and "W" for hardware Write Control ver-
sion.
Table 1. Signal Names
Note: WC signal is only available for ST24/25W04 products.
The ST24/25x04 are 4 Kbit electrically erasable
programmable memories (EEPROM), organized
as 2 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
ance of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2 C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2 C bus defini-
tion. This is used together with 2 chip enable inputs
(E2, E1) so that up to 4 x 4K devices may be
attached to the I2 C bus and selected individually.
The memories behave as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
DESCRIPTION (cont’d)
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
2/16
ST24/25C04, ST24/25W04
Notes:1. X = VIH or VIL Multibyte Write not available in ST24/25W04 versions.
Table 4. Operating Modes (1)
Note: The MSB b7 is sent first.
Table 3. Device Select Code
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E1 - E2). These chip enable inputs
are used to set the 2 least significant bits (b2, b3)
of the 7 bit device select code. These inputs may
be driven dynamically or tied to VCC or VSS to
establish the device select code.
Protect Enable (PRE). The PRE input pin, in ad-
dition to the status of the Block Address Pointer bit
(b2, location 1FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory area is not write protected.
3/16
ST24/25C04, ST24/25W04
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION2 C Bus Background
The ST24/25x04 support the I2 C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x04 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x04 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x04
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x04
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x04,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
SIGNAL DESCRIPTIONS (cont’d)
4/16
ST24/25C04, ST24/25W04
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
5/16
ST24/25C04, ST24/25W04
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the2 C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 2 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1. Thus up to 4 x 4K
memories can be connected on the same bus
giving a memory capacity total of 16 Kbits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 2
bits to its chip enable inputs E2, E1.
The 7th bit sent is the block number (one block =
256 bytes). The 8th bit sent is the read or write bit
(RW), this bit is set to ’1’ for read and ’0’ for write
operations. If a match is found, the corresponding
memory will acknowledge the identification on the
SDA bus during the 9th bit time.
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
AC MEASUREMENT CONDITIONS
Figure 4. AC Testing Input Output Waveforms
DEVICE OPERATION (cont’d)
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
6/16
ST24/25C04, ST24/25W04
Figure 5. AC Waveforms
Write Operations
The Multibyte Write mode (only available on the
ST24/25C04 versions) is selected when the MODE
pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynami-
cally with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac-
cess to one block of 256 bytes of the memory. After
receipt of the byte address the device again re-
sponds with an acknowledge.
For the ST24/25W04 versions, any write command
with WC = 1 will not modify the memory content.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.
7/16
ST24/25C04, ST24/25W04
Figure 6. I2 C Bus Protocol
Multibyte Write. For the Multibyte Write mode, the
MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the
memory. The master sends from one up to 4 bytes
of data, which are each acknowledged by the mem-
ory. The transfer is terminated by the master gen-
erating a STOP condition. The duration of the write
cycle is tW = 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 6 most significant address bits A7-
A2), the programming time is then doubled to a
maximum of 20ms. Writing more than 4 bytes in the
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes as soon as the first address of
these 8 bytes is the first address of the row, the 7
following bytes being written in the 7 following bytes
of this same row.
Page Write. For the Page Write mode, the MODE
pin must be at VIL. The Page Write mode allows up
to 8 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the 5 most significant mem-
8/16
ST24/25C04, ST24/25W04

Partno	Mfg	Dc	Qty	Available	Descript
24C04	FCS	N/a	340	avai	4KbitSerialI2CBusEEPROMwithUser-DefinedBlockWriteProtection
24C04. \|24C04	ATMEL	N/a	7416	avai	4KbitSerialI2CBusEEPROMwithUser-DefinedBlockWriteProtection