100355DC , Low Power Quad Multiplexer/LatchFeaturesThe 100355 contains four transparent latches, each of
100355DC
Low Power Quad Multiplexer/Latch
100355 Low Power Quad Multiplexer/Latch July 1989 Revised August 2000 100355 Low Power Quad Multiplexer/Latch General Description Features The 100355 contains four transparent latches, each ofGreater than 40% power reduction of the 100155 which can accept and store data from two sources. When2000V ESD protection both Enable (E ) inputs are LOW, the data that appears at n Pin/function compatible with 100155 an output is controlled by the Select (S ) inputs, as shown n Voltage compensated operating range = −4.2V to −5.7V in the Operating Mode table. In addition to routing data Available to industrial grade temperature range from either D or D , the Select inputs can force the out- 0 1 puts LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either D or D to an output. The Select inputs can be tied 0 1 together for applications requiring only that data be steered from either D or D . A positive-going signal on either 0 1 Enable input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100355PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100355QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100355QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names Description E , E Enable Inputs (Active LOW) 1 2 S , S Select Inputs 0 1 28-Pin PLCC MR Master Reset D –D Data Inputs na nd Q –Q Data Outputs a d Q –Q Complementary Data Outputs a d © 2000 DS010147
