100351QC ,Low Power Hex D-Type Flip-FlopFeaturesThe 100351 contains six D-type edge-triggered, master/
100351PC-100351QC-100351QCX-100351QI
Low Power Hex D-Type Flip-Flop
100351 Low Power Hex D-Type Flip-Flop July 1988 Revised August 2000 100351 Low Power Hex D-Type Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/40% power reduction of the 100151 slave flip-flops with true and complement outputs, a pair of2000V ESD protection common Clock inputs (CP and CP ) and common Master a b Pin/function compatible with 100151 Reset (MR) input. Data enters a master when both CP a Voltage compensated operating range: and CP are LOW and transfers to the slave when CP and b a −4.2V to −5.7V CP (or both) go HIGH. The MR input overrides all other b Available to industrial grade temperature range inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names Description D –D Data Inputs 0 5 CP , CP Common Clock Inputs a b MR Asynchronous Master Reset Input Q –Q Data Outputs 0 5 Q –Q Complementary Data Outputs 0 5 © 2000 DS009885
