100331DC , Low Power Triple D-Type Flip-FlopFeaturesThe 100331 contains three D-type, edge-triggered master/
100331DC
Low Power Triple D-Type Flip-Flop
100331 Low Power Triple D-Type Flip-Flop February 1990 Revised August 2000 100331 Low Power Triple D-Type Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/35% power reduction of the 100131 slave flip-flops with true and complement outputs, a Com-2000V ESD protection mon Clock (CP ), and Master Set (MS) and Master Reset CPin/function compatible with 100131 (MR) inputs. Each flip-flop has individual Clock (CP ), n Voltage compensated operating range = −4.2V to −5.7V Direct Set (SD ) and Direct Clear (CD ) inputs. Data enters n n Available to industrial grade temperature range a master when both CP and CP are LOW and transfers n C to a slave when CP or CP (or both) go HIGH. The Master n C Set, Master Reset and individual CD and SD inputs over- n n ride the Clock inputs. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number Package Description 100331SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100331PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100331QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100331QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pin Descriptions Pin Names Description 28-Pin PLCC CP –CP Individual Clock Inputs 0 2 CP Common Clock Input C D –D Data Inputs 0 2 CD –CD Individual Direct Clear Inputs 0 2 SD Individual Direct Set Inputs n MR Master Reset Input MS Master Set Input Q -Q Data Outputs 0 2 Q –Q Complementary Data Outputs 0 2 © 2000 DS010262
