100331 ,Low Power Triple D Flip-Flop100331LowPowerTripleDFlip-FlopJuly1992100331LowPowerTripleDFlip-FlopGeneralDescription
100331 ,Low Power Triple D Flip-Flop
100331DC , Low Power Triple D-Type Flip-FlopFeaturesThe 100331 contains three D-type, edge-triggered master/
100331
Low Power Triple D Flip-Flop
TL/F/10262
Low
Power
Triple
Flip-Flop
July 1992
Low Power TripleD Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with trueand complement outputs,a Com-
mon Clock (CPC), and MasterSet (MS)and Master Reset
(MR) inputs. Each flip-flophas individual Clock (CPn), Direct
Set (SDn) andDirect Clear (CDn) inputs. Data entersa mas-
ter when both CPn and CPCare LOW and transferstoa
slave when CPnor CPC(or both)go HIGH.The MasterSet,
Master Reset and individual CDn and SDn inputs override
the Clock inputs.All inputs have50kX pull-down resistors.
Features 35% power reductionofthe 100131 2000V ESD protection Pin/function compatible with 100131 Voltage compensated operating range eb4.2Vto
b5.7V Availableto industrial grade temperature range Availableto MIL-STD-883
Logic Symbol
TL/F/10262–1
Pin Names Description
CP0–CP2 IndividualClock Inputs
CPC CommonClock Input
D0–D2 Data Inputs
CD0–CD2 IndividualDirect Clear Inputs
SDn IndividualDirectSet Inputs Master Reset Input MasterSet Input
Q0-Q2 Data Outputs
Q0–Q2 ComplementaryData Outputs
Connection Diagrams
24-Pin DIP/SOIC
TL/F/10262–2
28-PinPCC
TL/F/10262–4
24-PinQuad Cerpak
TL/F/10262–3
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
