100201 ,Low Power 2-Input OR/NOR Gate/Inverter
10025026-10003TLF , PCI EXPRESS STRADDLE MOUNT CARD EDGE ASSY
100301PC ,Low Power Triple 5-Input OR/NOR Gate
100301PC ,Low Power Triple 5-Input OR/NOR Gate
100301PC ,Low Power Triple 5-Input OR/NOR Gate
100302DC , Low Power Quint 2-Input OR/NOR Gate
14001B ,B-Suffix Serise CMOS GatesMaximum Ratings are those values beyond which damage to the device may occur.tTemperature Derating: ..
1403 ,Bulk Metal Foil Technology, 4 Pin Transistor Outline Hermetic Resistor Network, Smallest Available Miniature Hermetically-Sealed Network Applications EngineeringDepartment. (See data sheet “Network Worksheet.”) A uniquepart number wil ..
1-406541-7 , INVERT MOUDULAR JACK ASSEMBLY 1 X 1, SHIELDED, PANEL GROUND
1414C , Type 12 Mild Steel Junction Box 1414 Series
1417 ,Bulk Metal Foil Technology, 8 Pin Transistor Outline Hermetic Resistor Network, Alternative Layout to Model 1413Applications Engineering Department.(See data sheet “Network Worksheet.”) A unique part number wil ..
14174B , Hex Type D Flip-Flop
100201
Low Power 2-Input OR/NOR Gate/Inverter
100201 Low Power 2-Input OR/NOR Gate/Inverter June 1992 Revised November 1999 100201 Low Power 2-Input OR/NOR Gate/Inverter General Description Features The 100201 is a 2-input OR/NOR Gate and a singleSmall 8 lead 150 mil SOIC package Inverter Gate in an eight pin SOIC package. All inputs have2000V ESD protection 50 kΩ pull-down resistors and all outputs are buffered. The 300 MHz minimum F toggle 100201 is ideal for single gate needs or for use as the feed- Temperature compensated back loop of a crystal oscillator circuit. Voltage compensated operating range = −4.2V to −5.7V V EE Ordering Code: Order Number Package Number Package Description 100201SC M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.50” Narrow Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description D , D , D Data Inputs a 1b 2b O Data Outputs b O , O Complementary Data Outputs a b © 1999 DS011000
