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tc554161fti-85l
262,144-WORD BY 16-BIT STATIC RAM
TOSHIBA TC554161FTl-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT STATIC RAM
D E S C R I PT I O N
The TC554161FTI is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5 V
i 10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 10 mA/MHz (typ) and a minimum cycle time of 85 ns. It is automatically placed in low-power mode
at 200 PA standby current (max) when chip enable (CE) is asserted high. Thge are two control inputs. CE is
used to select the device and for data retention control, and output enable (OE) provides fast memory access.
Data byte control pin (tTrf, trg) provides lower and upper byte access. This device is well suited to various
microprocessor system applications where high speed, low power and battery backup are required. And, with a
guaranteed operating range of - 40° to 85°C, the TC554161FTI can be used in environments exhibiting
extreme temperature conditions. The TC554161FTI is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATU RES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 55 mW/MHz (typical) TC554161FTI
0 Standby current of 8 pLk (maximum) at -85L -10L
Ta = 25°C Access Time 85 ns 100 ns
ct Single power supply voltageif5 V , 10% E Access Time 85 ns 100 ns
0 Power down features using CE. to-E Access Time 45 ns 50 ns
0 Data retention supply voltage of 2 to 5.5 V
0 Direct TTI, compatibility for all inputs and outputs
0 Wide operating temperature range of - 40° to 85°C
0 Package:
TSOP II 54-P-400-0.80 (FTI) (Weight: 0.55 g typ)
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
NC L IO 54 3 A4 A0 to A17 Address Inputs
A3 E 2 53 II A5
A2 L 3 52 JA6 I/OI to_|/O16 Data Inputs/Outputs
A1 E 4 51 :1 A7 CE Chip Enable
A0 E 5 50 I NC .
I/O16 L 6 49 Cl l/OI 12va Read/Write Control
l/O15 L 7 48 Cl I/O2 OE Output Enable
VDD E 8 47 J VDD E, W Data Byte Control Input
GND E 9 46 Cl GND
HOME 10 45 Cl I/O3 VDD Power (+ 5V)
|/O1_3 L 11 44 II @4 GND Ground
U_BE 12 43 HQ .
CE E 13 42 Cl OE NC No Connection
OP E 14 41 II OP OP* Option
Um L i2 li J li, *: OP pin must be open or connected to GND.
l/O11 E 17 38 J I/O6
GND E 18 37 :lGND
l/O10 L 20 35 Cl I/O?
|/09 E 21 34 Cl l/O8
NC L 22 33 3A8
A17 L 23 32 3A9
A16 E 24 31 3A10
A15 E 25 30 3A11
A14 L 26 29 3A12
A13 L 27 28 C) NC
(Normal pinout)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-12 1/9
TOSHIBA
BLOCK DIAGRAM
DECODER
>>>>222222
O—‘NWNWhU’ImN
BUFFER
GENERATOR
MEMORY
TC554161 FTI-85L,-10L
A-o GND
CELL ARRAY
1,024 x 256 x
(4,194,304)
SENSE AMP
COLUMN
DECODER
COLUMN
OUTPUT
BUFF ER
OUTPUT
BUF FER
ADDRESS BUFFER
A4 A6 A8 A10
A5 A7 A9 A11
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - 0.3 * to 7.0 V
VI/O Input/Output Voltage - 0.5 * to VDD + 0.5 V
PD Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg Storage Temperature - 55 to 150 °C
Topr Operating Temperature - 40 to 85 'C
* - 3.0 V when measured at a pulse width of 30 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5 V
" Input High Voltage 2.4 - VDD + 0.3 V
VIL Input Low Voltage - 0.3 * - 0.6 V
VDH Data Retention Supply Voltage 2.0 - 5.5 V
* - 3.0 V when measured ata pulse width of 30 ns
1997-06-12 2/9
TOSHIBA TC554161FTl-85L,-10L
DC CHARACTERISTICS(Ta = - 40° to 85°C, VDD = SV i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VIN = 0V to VDD - - i 1.0 prA
C-E = V = V o-E = V
Lo Output Leakage Current C IH or W IL or O IH - - , 1.0 ,uA
VOUT = 0V to VDD
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
E = " min - - 100
bool W = VIH! IOUT = 0 mA Tcycle mA
Other Inputs = VIHNIL 1 M; - 15 -
Operating Current -
CE = 0.2V min - - 90
'DDOZ W = VDD - 0.2 v, IOUT = 0 mA Tcycle mA
Other Inputs = VDD - 0.2 V/0.2V Irs - 10 -
|DDS1 E = " - - 3 mA
I Standby Current E = VDD - 0.2V Ta = 25°C - 4 8 A
DDS? VDD = 2.0 to 5.5V Ta = - 40° to 85°C - - 140 ’1
CAPACITANCE (Ta = 25°c,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE EE tri? R/W CIT UE l/OI to l/O8 I/O9 to l/O16 POWER
L L Output Output IDDO
Read L L H H L High-Z Output IDDO
L H Output High-Z IDDO
L L Input Input IDDO
Write L x L H L High-Z Input IDDO
L H Input High-Z IDDO
L H H x x
Outputs Disable High-Z High-Z IDDO
L x x H H
Standby H x x x x High-Z High-Z IDDS
x = don't care
H = logic high
L = logiclow
1997-06-12 3/9
TOSHIBA TC554161FTl-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 5 V i 10%)
READ CYCLE
TC554161FTI
SYMBOL PARAMETER -85L -10L UNIT
MIN MAX MIN MAX
tRC Read Cycle Time 85 - 100 -
tACC Address Access Time - 85 - 100
tco Chip Enable Access Time - 85 - 100
tog Output Enable Access Time - 45 - 50
tBA Data Byte Control Access Time - 45 - 50
tOH Output Data Hold Time 10 - 10 -
tcoE Chip Enable Low to Output Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - O -
tBE Data Byte Control Low to Output Active 0 - 0 -
too Chip Enable High to Output High-? - 35 - 40
tom Output Enable High to Output High-Z - 35 - 40
tBD Data Byte Control High to Output High-Z - 35 - 40
WRITE-CYCLE
TC554161FTI
SYMBOL PARAMETER -85L -10L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 55 - 60 -
tcw Chip Enable to End of Write 70 - 80 -
th Data Byte Control to End of Write 55 - 60 -
tas Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
tos Data Setup Time 35 - 40 -
tDH Data Hold Time 0 - O -
toew MN High to Output Active 0 - O -
tODw R/W Low to Output High-Z - 35 - 40
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.6 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, tF: 5 ns
1997-06-12 4/9
TOSHIBA TC554161FTl-85L,-10L
TIMING DIAGRAMS
ADDRESS
Dout VALID DATA OUT
IND ERMINATE
WRITE CYCLE 1 jR/W CONTROLLED) (See Note 4)
ADDRESS X X
tas ’ twp - tWR
RNV hrs, _ /
CE "N vp"
W, LE "As, A"
tODW tOEW
Dout (See Note 2) A (See Note 3)
I tos toc
Din (See Note 5) X VALID DATA IN X (See Note 5)
1997-06-12 5/9
TOSHIBA TC554161FTl-85L,-10L
WRITE CYCLE 2 LEE- CONTROLLED) (See Note 4)
ADDRESS X X
tas twp twit
R/W "A, y?
E te, 'RS, ,
mm ptr"
Dout y
tos tDH
Din (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (W, E CONTROLLED) (See Note 4)
ADDRESS X X
JAS, 4 twp _ 4 tum _
R/IN \ 2%
tTl? h 2/
mm 'ii) _ /
Dout A
tos tDH
Din (See Note 5) VALID DATA IN (See Note 5)
1997-06-12 6/9
TOSHIBA TC554161FTl-85L,-10L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high
impedance.
(3) If tTrif goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at
high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
1997-06-12 7/9
TOSHIBA
DATA RETENTION CHARACTERISTICS (Ta = - 40° to 85°C)
TC554161 FTI-85L,-10L
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
VDH = 3.0V - - 70*
box Standby Current pA
VDH = 5.5V - - 140
tCDR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
UECONTROLLED DATA RETENTION MODE
6pA(max) at Ta = - 40° to 40°C
VDD -1 DATA RETENTION MODE
4.5 v - - - - - ---_
(See Note)
(See Note)
" - - - l
- / VDD - 0.2 V
CE 4 tCDR
Note: When CE is operating at the VIH level (2.4 V), the operating current is given by IDDSl during
the transition of VDD from 4.5 V to 2.6 V.
1997-06-12 8/9
TOSHIBA TC554161FTl-85L,-10L
PACKAGE DIMENSIONS (TSOPII 54-P-400-O.80)
Units in mm
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L 22.62MAX
l 22.22101 iijli:' 2.
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01:0 05
0.5i0.1
Weight: th55g (typ)
1997-06-12 9/9
www.ic-phoenix.com
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