| Partno |
Mfg |
Dc |
Qty |
Available | Descript |
| X9317UV8I-2.7 |
MIC |
N/a |
245 |
 |
Low Noise, Low Power, 100 Taps |
| X9317UV8I-2.7 |
XILNX|Xilinx |
N/a |
150 |
|
Low Noise, Low Power, 100 Taps |
X9317UV8I-2.7T1 XICOR
X9317UV8I-2.7T2 INTERSIL
X9317UV8I-27T1 XICOR
X9317UV8IZ-2.7T1 INTERSIL
X9317UV8ZT1 XICOR
X9317W XIC
X9317W INTERSIL
X9317W XICOR
X9317WF XICOR
X9317WG XICOR
X9317WI INTERSIL
X9317WM8 XICOR, Low Noise, Low Power, 100 Taps
X9317WM8 INTERSIL , Low Noise, Low Power, 100 Taps
X9317WM8-2.7 INTERSIL , Low Noise, Low Power, 100 Taps
X9317WM8-2.7 XICOR, Low Noise, Low Power, 100 Taps
X9317WM8I XICOR, Low Noise, Low Power, 100 Taps
X9317WM8I XIOCR, Low Noise, Low Power, 100 Taps
X9317WM8I INTERSIL , Low Noise, Low Power, 100 Taps
X9317WM8I-2.7 XICOR, Low Noise, Low Power, 100 Taps
X9317WM8I-2.7 INTERSIL, Low Noise, Low Power, 100 Taps
X9317WM8IZ intersil, Digitally Controlled Potentiometer (XDCP™)
X9317WM8IZ-2.7 INTERSIL, Digitally Controlled Potentiometer (XDCP™)
X9317WM8Z-2.7 INTERSIL , Digitally Controlled Potentiometer (XDCP™)
X9317WM8Z-2.7 INTERSIL, Digitally Controlled Potentiometer (XDCP™)
X9317UV8I-2.7 , Low Noise, Low Power, 100 Taps
X9317WP , Low Noise, Low Power, 100 Taps
X9317WP , Low Noise, Low Power, 100 Taps
X9317WP-2.7 , Low Noise, Low Power, 100 Taps
X9317WS8IZ-2.7 , Digitally Controlled Potentiometer (XDCP™)
XC7336 ,36-Macrocell CMOS EPLDblock diagram ofcan be individually controlled by one of two dedicatedthe High-Density FB is shown ..
XC7336-15 ,36-Macrocell CMOS EPLDfeatures a power-management scheme The XC7336 has a multibit security system that controlswhich per ..
XC7336-7 ,36-Macrocell CMOS EPLDBlock Diagram2-23This document was created with FrameMaker402AND ARRAY AND ARRAYAND ARRAY AND ARRAY ..
