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TVP7001PZPTI/BBN/a64avaiTriple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70
TVP7001PZPRTIN/a1avaiTriple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70


TVP7001PZP ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70SLES164–FEBBRUARY 2006TERMINAL ASSIGNMENTSSOGIN_1 1 75 SDAGIN_1 2 74 SCLA18GND 3 73 I2CAA18VDD 4 72 ..
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TVP7002PZP ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70 SLES206C –MAY 2007–REVISED APRIL 2013Terminal AssignmentsSOGIN_1 1 75 SDAGIN_1 2 74 SCL73AGND 3 I2 ..
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TVP7002PZPR ,Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70FEATURES23• Analog Channels • Output Formatter– –6-dB to 6-dB Analog Gain – Supports 20-bit 4:2:2 O ..
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TVP7001PZP-TVP7001PZPR
Triple 8/10-bit, 165/110MSPS Video ADC 100-HTQFP 0 to 70
www.ti.com
FEATURES APPLICATIONS
DESCRIPTION
TVP7001
SLES164–FEBBRUARY 2006
TRIPLE 8/10-BIT, 165/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
LCD TV/Monitors/Projectors Analog Channels DLP TV/Projectors–-6 dBto6 dB Analog Gain PDP TV/Monitors– Analog Input MUXs PCTV Set-Top Boxes– Auto Video Clamp Digital Image Processing– Three Digitizing Channels, Each With Video Capture/Video EditingIndependently Controllable Clamp, PGA, Scan Rate/Image Resolution Convertersand ADC Video Conferencing– Clamping: Selectable Clamping Between Video/Graphics Digitizing EquipmentBottom Level and Mid-level Offset: 1024-Step Programmable RGBor
YPbPr Offset Control

TVP7001isa complete solution for digitizing video– PGA: 8-Bit Programmable Gain Amplifier and graphic signalsin RGBor YPbPr color spaces.– ADC: 8/10-Bit 165/110 MSPS A/D Converter The device supports pixel rates up to 165 MHz.– Automatic Level Control Circuit Therefore,it can be used for PC graphics digitizingto the VESA standardof UXGA (1600× 1200)– Composite Sync: Integrated Sync-on-Green
resolutionat 60 Hz screen refresh rate, andin videoExtraction From GreenLuminance Channel environments for the digitizingof digital TV formats,– Support for DC and AC-Coupled Input including HDTV upto 1080p. TVP7001 can be usedSignals to digitize CVBS and S-video signal with 10-bit ADCs.• PLL The TVP7001is powered from 3.3-V and 1.8-V– Fully Integrated Analog PLL for Pixel Clock supply and integratesa triple high-performance A/DGeneration converter with clamping functions and variable gain,
independently programmable for each channel. The– 12-165 MHz Pixel Clock Generation From
clamping timing windowis provided by an externalHSYNC Input pulseor can be generated internally. The TVP7001– Adjustable PLL Loop Bandwidth for includes analog slicing circuitryon theYorG inputtoMinimum Jitter support sync-on-luminance or sync-on-green– 5-Bit Programmable Subpixel Accurate extraction.In addition, TVP7001 can extract discrete
Positioningof Sampling Phase
HSYNC and VSYNC from composite sync usinga
sync slicer.• Output Formatter Support for RGB/YCbCr 4:4:4 and YCbCr TVP7001 also containsa complete analog PLL block generatea pixel clock from the HSYNC input. Pixel4:2:2 Output Modesto Reduce Board Traces
clock output frequencies range from 12 MHzto 165– Dedicated DATACLK Output for Easy MHz.Latchingof Output Data
All programming of the part is done via an industry-standardI2C interface, which supports both Normal/FastI2C Interface reading and writingof register settings. The TVP7001 Register Capability
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