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TSB41LV04APFPTIN/a1073avaiIEEE 1394a Four-Port Cable Transceiver/Arbiter


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TSB41LV04APFP
IEEE 1394a Four-Port Cable Transceiver/Arbiter
Fully Compliant With OpenHCIRequirements Provides Four P1394a Fully-Compliant
Cable Ports at 100/200/400 Megabits per
Second (Mbits/s)
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
Extended Resume Signaling for
Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy
in Battery-Powered Applications Include:
Automatic Device Power-Down during
Suspend, Device Power-Down Terminal,
Link Interface Disable Via LPS, and Inactive
Ports Powered-Down
Ultralow-Power Sleep Mode Node Power Class Information Signaling
for System Power Management
Cable Power Presence Monitoring Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
Interface to Link-Layer Controller Supports
Low-Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies
Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies
Low-Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Incoming Data Resynchronized to Local
Clock
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
Separate Cable Bias (TPBIAS) for Each Port Single 3.3-V Supply Operation Low-Cost High-Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package


description

The TSB41LV04A provides the digital and analog transceiver functions needed to implement a four-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV04A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
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