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TS507CDTSTN/a14990avaiHigh precision single supply rail to rail op-amp


TS507CDT ,High precision single supply rail to rail op-ampAbsolute maximum ratings (AMR)Symbol Parameter Value Unit(1)V Supply voltage 6CC(2)V Differential i ..
TS507ID ,High Precision Rail-to-Rail Operational AmplifierTS507High Precision Rail-to-Rail Operational AmplifierPRELIMINARY DATA

TS507CDT
High precision single supply rail to rail op-amp
March 2013 DocID10958 Rev 6 1/20
TS507

High precision rail-to-rail operational amplifier
Datasheet - production data
Features
Ultra low offset voltage: 25 µV typ, 100 µV max Rail-to-rail input/output voltage swing Operates from 2.7 V to 5.5 V High speed: 1.9 MHz 45° phase margin with 100 pF Low consumption: 0.8 mA at 2.7 V Very large signal voltage gain: 131 dB High-power supply rejection ratio: 105 dB Very high ESD protection 5kV (HBM) Latchup immunity Available in SOT23-5 micropackage Automotive qualification
Applications
Battery-powered applications Portable devices Signal conditioning Medical instrumentation
Description

The TS507 is a high performance rail-to-rail
input/output amplifier with very low offset voltage.
This amplifier uses a new trimming technique that
yields ultra low offset voltages without any need
for external zeroing.
The circuit offers very stable electrical
characteristics over the entire supply voltage
range, and is particularly intended for automotive
and industrial applications.
The TS507 is housed in the space-saving 5-pin
SOT23 package, making it well suited for battery-
powered systems. This micropackage simplifies
the PC board design because of its ability to be
placed in small spaces (external dimensions are
2.8 mm x 2.9 mm).
Contents TS507
2/20 DocID10958 Rev 6
Contents Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Out-of-the-loop compensation technique . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 In-the-loop-compensation technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 SOT23-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 SO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID10958 Rev 6 3/20
TS507 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions



Table 1. Absolute maximum ratings (AMR)
Value with respect to VDD pin. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. VCC-Vin and Vin must not exceed 6 V. Short-circuits can cause excessive heating and destructive dissipation. Rthja/c are typical values. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are floating. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins.
Table 2. Operating conditions
Value with respect to VDD pin. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
Electrical characteristics TS507
4/20 DocID10958 Rev 6
2 Electrical characteristics

Table 3. Electrical characteristics at VCC = +5 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1)
DocID10958 Rev 6 5/20
TS507 Electrical characteristics
All parameter limits at temperatures different from 25 ° C are guaranteed by correlation. Measurements made at 4 Vicm values: Vicm=0 V, Vicm=3.8 V, Vicm=4.2 V, Vicm=5 V.
Table 3. Electrical characteristics at VCC = +5 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1) (continued)
Electrical characteristics TS507
6/20 DocID10958 Rev 6
Table 4. Electrical characteristics at VCC = +3.3 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1)
DocID10958 Rev 6 7/20
TS507 Electrical characteristics
All parameter limits at temperatures different from 25 ° C are guaranteed by correlation. Measurements done at 4 Vicm values: Vicm=0 V, Vicm=2.1 V, Vicm=2.5 V, Vicm=3.3 V.
Table 4. Electrical characteristics at VCC = +3.3 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1) (continued)
Electrical characteristics TS507
8/20 DocID10958 Rev 6
Table 5. Electrical characteristics at VCC = +2.7 V VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1)
DocID10958 Rev 6 9/20
TS507 Electrical characteristics
All parameter limits at temperatures different from 25 ° C are guaranteed by correlation. Measurements done at 4 Vicm values: Vicm=0 V, Vicm=1.5 V, Vicm=1.9 V, Vicm=2.7 V.
Table 5. Electrical characteristics at VCC = +2.7 V VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C,
RL connected to VCC/2 (unless otherwise specified)(1) (continued)
Electrical characteristics TS507
10/20 DocID10958 Rev 6



Figure 1. Input offset voltage distribution for
Vicm≤
VCC-1.2 V at T=25 °C
Figure 2. Input offset voltage distribution vs.
temperature for Vicm≤
VCC-1.2 V
Figure 3. Input offset voltage distribution vs.
temperature for Vicm ≥ VCC-0.8 V
Figure 4. Input offset voltage distribution for
Vicm ≤
VCC-1.2 V at T=25 °C after HTB
Figure 5. Input offset voltage distribution for
Vicm ≤
VCC-1.2 V at T=25 °C after THB
Figure 6. Input offset voltage vs. input common
mode voltage at T=25 °C
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