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TPD7100F
2ch HIGH-SIDE N-ch POWER MOSFET GATE DRIVER
TOSHIBA TPD7100F
TENTATIVE TOSHIBA INTELLIGENT POWER DEVICE
SILICON MONOLITHIC POWER MOS INTEGRATED CIRCUIT
TPDril00F
2ch HIGH-SIDE N-ch POWER MOSFET GATE DRIVER
The TPD7100F is a 2ch High-side N-ch Power MOSFET Gate
Driver. This IC contains a power MOSFET driver and power
MOSFET protective and diagnostic functions, allowing you
to configure a high-side switch for large-current
applications easily.
FEATURES
0 The large-current charge pump allows for fast switching.
o Power MOSFET protective and diagnostic functions are built-in.
Protective functions : Overvoltage
(internal device protection),
overcurrent protection, VDD
voltage drop detection
* Overvoltage is internally limited. No detection or SSOP24-P-300-1.00B
shutdown functions are included. . .
Diagnostic functions: Overcurrent Weight ' 0.29g (Typ.)
o The level of Overcurrent detection can set by external resistor.
0 Package .' SSOP-24 (300 mil) with embossed-tape packing
Because this product uses MOS structure, must take special care with electrostatic when
handling.
PIN ASSIGNMENT MARKING
(TOP VIEW) Toshiba Trademark
CP2-1 Eloo, omnrrfinrunnrunn
_ 2 23 p"
CPI E 3va tr |:| --- Lot code
CPI + E El Rref
CP2+ E 2C1lmsrefl T P D 7 1 0 0 F -- Product no.
CPV+ E El Rlsref2
N.c.lE C9lws LlULlLlULlULlLlLlLlLl
VGS1 E EDIAGH Lot code naming system
Vsense1 E E] DIAG1-1 El El El El Cl
LToshiba house no.
V652 E ED'AGZ'Z Tii- ()elte,c,tduirgti week (52 weeks f", 53
10 15 _ wee s in icating system starting rom
Vsense2 I: Cs] DIAG2-1 the first Thursday of January)
GND IE Elm Manufactured year (last two digits of
the year)
GND 12 EINZ
980910EBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
o The information contained herein is presented only as a guide for the ap Iications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
o T e information contained herein is subject to change without notice.
2000-02-22 1/8
TOSHIBA
TENTATIVE
BLOCK DIAGRAM
TPD71OOF
DIAG1-1
DIAG1-2
64 Input logic !
Rref lset circuit
Rref Cl
Cui. #4...
DIAG2-1 i i
DIAG2-2
(ii I Input logic
I Mask
Charge pump
Latch circuit
VGSI cr,
Vsense1
Level shift circuit d
-
RISref1 RIS f1
VGS2 3
Vsense2
RISref2
2000-02-22 2/8
TOSHIBA
TPD710OF
TENTATIVE
PIN DESCRIPTION
PIN NO. SYMBOL PIN DESCRIPTION
1 CP2- Negative side connecting pin for the charge pump's second capacitor.
2 CP1 - Negative side connecting pin for the charge pump's first capacitor.
3 CP1 + Positive side connecting pin for the charge pump's first capacitor.
4 CP2+ Positive side connecting pin for the charge pump's second capacitor.
Positive side connecting pin for the charge pump's third capacitor. Although
5 CPV+ about three times the VDD voltage is generated, it is limited about
28V by a voltage clamping circuit.
6 N.C. -
External power MOSFET gate drive pin for CM. This pin controls the external
7 VGS1 power MOSFET. Also, when overcurrent flows in the external power MOSFET, it
shuts down the gate and is latched. It is unlatched by a low on input.
External power MOSFET monitor pin for ch1 : overcurrent is detected by
8 Vsense1 comparing the difference between this and the VDD2 pin with the reference
voltage.
External power MOSFET gate drive pin for ch2. This pin controls the external
9 V652 power MOSFET. Also, when overcurrent flows in the external power MOSFET, it
shuts down the gate and is latched. It is unlatched by a low on input.
External power MOSFET monitor pin for ch2 : overcurrent is detected by
10 Vsense2 comparing the difference between this and the VDD2 pin with the reference
voltage.
11 GND Ground pin : shared internally with pin 12.
12 GND Shared internally with pin 11.
13 IN2 Input pin for ch2 (active high) : This pin has a pull-down resistor (100 kfl typ.),
so that even when it is open-circuited, output will not turn on inadvertently.
14 INI Input pin for CM (active high) : This pin has a pull-down resistor (100 k0 typ.),
so that even when it is open-circuited, output will not turn on inadvertently.
Diagnostic output pin for ch2 (N-ch open-drain) : when overcurrent condition is
15 DIAG2-1 detected, its output goes low. Also, when overcurrent is detected, it remains
latched until the next rising edge of input.
Diagnostic output pin for ch2 (N-ch open-drain) : by comparing the voltage
16 DIAG2-2 between VDD2 and Vsense2 pins with the set overcurrent level, it outputs
external power MOSFET on/off state.
Diagnostic output pin for ch1 (N-ch open-drain) : when overcurrent condition is
17 DlAG1-1 detected, its output goes low. Also, when overcurrent is detected, it remains
latched until the next rising edge of input.
Diagnostic output pin for chl (N-ch open-drain) : by comparing the voltage
18 DlAG1-2 between VDD2 and Vsense1 pins with the set overcurrent level, it outputs
external power MOSFET on/off state.
Chip inhibit pin (active low) : By driving this pin high, all outputs can be
19 W turned off regardless of input signals. This pin has a pull-up resistor (100 kfl
typ.).
2000-02-22 3/8
TOSHIBA TPD71OOF
TENTATIVE
PIN NO. SYMBOL PIN DESCRIPTION
Overcurrent detection level setup pin for ch2 : the voltage determined by the
20 RISref2 constant current set by the resistor connected to the Rref pin and the
resistance of an external resistor connected to the RISref2 pin is referenced to
detect overcurrent.
Overcurrent detection level setup pin for chl : the voltage determined by the
21 RlSref1 constant current set by the resistor connected to the Rref pin and the
resistance of an external resistor connected to the RlSref1 pin is referenced to
detect overcurrent.
Resistor connection pin ;
22 Rref This resistor determines the constant current used for the overcurrent detection
circuit. Connect 62 k0 (recommended) between this pin and GND.
23 VDD2 External power MOSFET drain voltage detection pin.
Power supply pin : the internal device is protected when overvoltage is
24 VDD1 applied.
MAXIMUM RATING (Ta = 25°C)
CHARACTERISTICS SYMBOL RATING UNIT
Power Supply Voltage VDD 30 V
Input Voltage VIN 0.5--6 V
Diagnosis Output Current IDIAG 2 mA
Power Dissipation PD 0.8 W
Operating Temperature Topr -40-110 °C
Strage Temperature Tstg - 55-150 "C
2000-02-22 4/8
TOSHIBA
TPD71OOF
TENTATIVE
ELECTRICAL CHARACTERISTICS (Unless otherwise specified : VDD = 8--18V, Tj = -40-110oC)
CHARACTERISTICS RATING PIN NO. TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply - -
Voltage VDD VDD 8 18 V
Supply Current IDD VDD 2:3? 2 3122:; VIN = ov, - - 10 mA
VIN(1) VDD = 12 V. VGS = "H" 3.5 - -
Input Voltage VIN (2) |N1, IN2 VDD = 12V, VGS = "L'' - - 1.5 V
IIN (1) lN1 Ibl2 VDD = 12 V, VIN = 5V - - 200
IIN (2) ' VDD = 12V, VIN = 0V -1 - 1
Input Current Im (1) W VDD = 12 v, vm = 5v -45 - - pA
1mm VDD--12V,VEt=--0V -250 - -
Vsense Vsense
Output Voltage VOH VDD - 12V, VIN - 5V - + 15* + 19* V
VOL V VDD = 12 V, VIN = 0V - - 0.4
GSI VDD = 12 v, VIN = 5v,
IOH V552 CP = 0.01 pF - 0.1 -
Output Current VDD - 12V VIN - 0V A
IOL CP = 0.01PF - 0.1 -
Overcurrent Detection RISref RISref - 10 20 40 k0
Resistance Setup Range
Pnstap.t Current Source VRref Rref Rref = 62 k0 1.17 1.30 1.43 v
Setup Pin Voltage
Rref = 62 kn,
VDS (ON) (1) V RISref = 10 k0 0.16 0.20 0.24
Overcurrent Detection DD2 Rref = 62 kn,
Voltage VDs (ON) (2) $2233; mm = 20 k0 0.32 0.40 0.48 V
v Rref = 62 kn, 0 64 0 80 0 96
DS (ON) (3) RISref = 40 k0 . . .
Diagnostic Output VDD = 12 V,
Current IDH DIAG1 VDIAG = 5V - - IO W
Diagnostic Output DIAG2
Voltage VDL VDD - 12V, IDL - 1 mA - - 0.6 V
'loyTsup.p.ly. Drop VDDUVI- - 6.3 6.7 7.3
Detection Voltage V
Power Supply Drop DD V
Detection Reset Voltage VDDUVI + - 6.6 7.2 7.8
Undervoltage Protection 1/DDUV2 - - - 4.5
. . . t0N VGS1 - 2 5
V =12V, C = 3000 F
Switching Time tOFF VGS2 DD p - 2 5 ps
* : Vsense denotes the Vsense pin voltage.
Equation to calculate overcurrent detection resistance (RISref)
RISref = Rref x RDS (ON) x ID/VRref
= Rref x VDS (0N)/VRref
where RDS (ON)
VDS (ON) :
: ON-resistance of external power MOSFET
: drain current of external power MOSFET
: Rref pin voltage
ON-voltage of external power MOSFET
: external resistor connected to Rref pin (used to set constant current)
2000-02-22 5/8
TOSHIBA TPD71OOF
TENTATIVE
TRUTH TABLE
IN EITB VGS DIAG*-1 DlAG*-2 MODE
L H L H H
'l , II: n 3 When normal
H L H H (Note 1) L
L L L H H
H L H H (Note I) L For overvoltage
L L L L (Note 1/Note 2) H F
H L L L (Note 1) H or overcurrent
L L L H H When supply voltage
H L H H H drop detected
L L L H H Undervoltage
H L L H H protection
L L L H L When power MOSFET
H L H H L shorted
(Note 1) : Because overcurrent is detected by checking the drain-to-source voltage of the
power MOSFET, there is a possibility of detecting overcurrent erratically for a
while after input is driven high before the power MOSFET turns on, during which
the drain-to-source voltage is high. To prevent this erroneous detection, DIAG
detection is disabled for 15ps (typ.) by a mask circuit. This masking time depends
on the constant current determined by the internal capacitor and Rref. (The
masking time is 15ps when Rref = 62 kn.)
(Note 2) : After overcurrent is detected, DIAG remains latched until the next rising edge of
input.
TIMIMG CHART
Input Signal I
Overvoltage
detection
Overcurrent
detection
voltage detection
VDD under
voltage
protection
Power MOSFET
Output signal
VDD lowering I
W65 output voltage) t
DIAG*-1 signal
L_____________
F“ __________--____-_____.____._______________________
r____________m
F—— _-___ ____
DIAG*-2 signal I I L
I - L __________________
2000-02-22 6/8
TOSHIBA
TENTATIVE
APPLICATION CIRCUIT 1
Monitoring Power MOSFET drain-soure voltage
CPU OUT
APPLICATION CIRCUIT 2
TPD7100F
GND GND
Vsense G)--.
RlSref Cl.
TPD71OOF
3Nch power MOSFET
Monitoring voltage between shunt resistors (for detecting overcurrent with high accuracy)
CPU OUT
MOISTURE-PROOF PACKING
TPD7100F
Shunt resistor
Rshunt
3 Nch power MOSFET
RISref
After the pack is opened, use the devices in a 30°C, 60% RH environment, and within the 48 hours.
Embossed-tape packing cannot be baked. Devices so packed must be within their allowable time
limits after unpacking, as specified on the packing.
Tape packing quantity: 500 devices/reel (EL) or 2000 devices/reel (EL1)
2000-02-22 7/8
TOSHIBA TPD71OOF
TENTATIVE
PACKAGE DIMENSIONS
SSOP24-P-300-1.00B Unit : mm
fi4flFlFlfiilFlFlfiilflRFIFi "
6 OiO 2
8.0i0.3
£15? 'rssigyieei--------,
1.0TYP H 0.410.1_=m@
v, 13.5MAX t/
a 13.0:02 r/
cu. A e-.'c'cl.
ilk“ '?
1aosat,stccccsccci] 'it"' g ‘°
T''''" ,. 1",
_._.:L o
F- U'?,
Weight : 0.29g (Typ.)
2000-02-22 8/8
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