TP5116AJ ,7 V, monolithic CODECFunctional Description
Approximately 4 its after the rising edge of the XMIT SYNC
pulse, the vo ..
TP5116AJ ,7 V, monolithic CODECBlock Diagram
"
I SAMPLE AND “ I
ANALOG MPOT HOLD A/D SAR LOGIC DIGITAL OUTPUT
COMPARATOR ..
TP5116AJ ,7 V, monolithic CODECFeatures
The TP5116A and TP5156A are monolithic PCM CODECs TP5116A--wlaw coding (sign plus magni ..
TP5156AJ ,7 V, monolithic CODECapplications. Precision voltage reference on-chip
Each device contains separate WA and A/D circu ..
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TQM6M4022E , 3V Quad-Band GSM900 DCS Transmit Module
TQM6M4028E , 3V Dual-Band GSM900/DCS Transmit Module
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TP5116AJ-TP5156AJ
7 V, monolithic CODEC
TP5116A/TP5116A-1/TP5156A/TP5156A-1
National
Semiconductor
TP5116A, TP5116A-1, TP5156A, TP5156A-1
Monolithic CODECs
General Description
The TP5116A and TP5156A are monolithic PCM CODECs
implemented with double-poly CMOS technoiogy. The
TP5116A is intended for p-Iaw applications and the
TP5156A is for A-law applications.
Each device contains separate D/A and A/D circuitry. all
necessary sample and hold capacitors, and internal auto-
zero circuits. Each device also contains a precision internal
voltage reference, eliminating the need for an external refer-
ence. There are no internal connections to pins 15 or 16,
making them directly interchangeable with CODECs using
external reference components.
All devices are intended to be used with the TP3040 mono-
lithic PCM filter which provides the input anti-aliasing func-
tion for the encoder, smooths the output of the decoder and
corrects for the sin x/x distortion introduced by the decoder
sample and hold output.
Features
t 5V operation
TP5116A--qs-law coding (sign plus magnitude format)
TP5156A--A-law coding
Synchronous or asynchronous operation
Precision voltage reference on-chip
Internal sample-and-hold capacitors
Internal auto-zero circuit
Low operation power-40 mW typical
TTL compatible digital interface
Simplified Block Diagram
SAMPLE AND
ANALOG mpur ' SAR LOGiC . mm OUTPUT
HOLO V” COMPARATOR
" " R "
AW0-lER0 A- - xun CLOCK
- - xurr smc
REFERENCE CONTROL A-- MASTER cLocx
A---. tttY th0tht
= tttN smc
SAMPLE AND HOLD t
ANALOG OUTPUT - WA 352% q----. DIGITAL INPUT
l -.I-. t
ANALOG (N) oxcmu. cm) "
TL/H/6663-1
1 -202
Connection Diagram
DuaI-ln-Llne Package
Description of Pin Functions
Symbol
ANALOG INPUT
MASTER CLOCK
XMIT SYNC
XMIT CLOCK
DIGITAL OUTPUT
ANALOG INPUT- 1 16 -NC
"- 2 15 -NC
v--- 3 14 -ANALOG GROUND
NC-, 4 13 '-hNhu)t) OUTPUT
MASTER CLOCK- 5 12 -016fthL INPUT
XMH STNC-_ 6 11 i-DIGITAL GROUND
XMIT CLOCK- 7 10 FitCY CLOCK
DIGITAL OUTPUT- 8 9 F-ttty SYNC
TL/H/6663-2
Top Vlew
Order Number TP5116AJ or TP5156AJ
See NS Package NumberJ16A
Functlen Symbol Function
ANALOG INPUT to the encoder. This RCV SYNC Decoder frame sync pulse. Normally oc-
signal will be sampled at the beginning curring at an 8 kHz rate, this pulse is
of the encoder time siot and the result- nominally eight RCV CLOCK cycles
ing PCM code will be shifted out during wide.
the subsequent encode time slot. RCV CLOCK Receive bit clock input used to shift in
SW i 5%) Power Supply.
- 5V( * 5%) Power Supply.
Unused.
MASTER CLOCK input used to operate
the internal encode and decode se-
quencers. Should be 1.536 MHz,
1.544 MHz or 2.048 MHz.
Encoder frame sync pulse. Normally oc-
curring at an 8 kHz rate, this pulse is
nominally eight XMIT CLOCK cycles
Transmit bit clock input used to shift out
the PCM data on DIGITAL OUTPUT.
May operate from 64 kHz to 2.048 MHz.
May be asynchronous with RCV
CLOCK.
Serial PCM TFtl-STATE output from en-
coder. During the encoder time slot, the
PCM code for the previous sample of
ANALOG INPUT is shifted out, most
significant bit first, on the rising edge of
XMIT CLOCK.
the PCM data on DIGITAL INPUT. May
operate from 64 kHz to 2.048 MHz. May
be asynchronous with XMIT CLOCK.
DIGITAL GROUND All digital levels referenced to the DIGI-
DIGITAL INPUT
TAL GROUND pin.
Serial PCM data input to the decoder.
During the decoder time slot, PCM data
is shifted into DIGITAL INPUT, most sig-
nificant bit first, on the rising edge of
RCV CLOCK.
ANALOG OUTPUT ANALOG OUTPUT from the decoder.
ANALOG
GROUND
The decoder sample and hold amplifier
is updated approximately 15 ps after
the end of the decode time slot.
All analog signals are referenced to the
ANALOG GROUND pin.
l'VQSLSdll V99l9d1/l'V9I- LSdl/ V91 lSdl
TP5116A/TP5116A-1/TP5156A/TP5156A—1
ENCODING FORMAT AT DIGITAL OUTPUT
TP51 16A
Sign + Magnitude
TP5156A
(Includes Even Blt Inversion)
Functional Description
Approximately 4 us after the rising edge of the XMIT SYNC
pulse, the voltage present on the ANALOG INPUT is sam-
pled and the process of encoding that sample into a PCM
code is begun. Simultaneously, the 8-bit PCM code corre-
sponding to the previous sample is shifted out of the DIGI-
TAL OUTPUT, MSB first, on the rising edge of the next eight
cyctes of the XMIT CLOCK. When XMIT SYNC (which is
normally eight XMIT CLOCK cycles long) goes low, the TRI-
STATE DIGITAL OUTPUT is returned to the high imped-
ance state. On the TP5116A, the PCM code is in a p-law
sign plus magnitude format. The TP5156A uses the stan-
dard A-Iaw coding.
An 8-bit PCM code is shifted into DIGITAL INPUT on the
rising edge of the first eight RCV CLOCK pulses after RCV
SYNC goes high. RCV SYNC is nominally eight RCV
CLOCK cycles wide. Approximately 15 MS after RCV SYNC
goes low, the ANALOG OUTPUT is updated to the voltage
corresponding to the PCM input code.
All encoding and decoding operations are run from the
MASTER CLOCK. MASTER CLOCK should be in the range
of 1.536 MHz to 2.048 MHz and must be synchronous with
XMIT CLOCK. The XMIT and RCV CLOCK may vary from 64
kHz to 2.048 MHz.
" = +FuIl-Scale 1 1 1 1 1 1 1 1 1 o 1 o 1 o 1 o
v = OV {1 o o o o o o o 1 1 o 1 o 1 o 1
IN o o o o o o o o o 1 o 1 o 1 o 1
vm = -Full-Scale o 1 1 1 1 1 1 1 o o 1 o 1 o 1 o
ENCODING DELAY
The encoding process begins immediately at the beginning
of the encode time slot and is concluded no later than 18
time slots later. In normal applications, the PCM data is not
shifted out until the next time slot 125 us later, resulting in
an encoding delay of 125 p.S. In some applications it is pos-
sible to operate the CODEC at a higher frame rate to reduce
this delay. With a 2.048 MHz MASTER CLOCK, the FS rate
could be increased to 15 kHz, reducing the delay from 125
its to 67 ps.
DECODING DELAY
The decoding process begins immediately after the end of
the decoder time slot. The output of the decoder sample
and hold amplifier is updated 28 MASTER CLOCK cycles
later. The decoding delay is therefore approximately 28
clock cycles plus one half of a trame time or, 81 M5 for a
1.544 MHz system with an 8 kHz frame rate or, 76 p.s for a
2.048 MHz system with an 8 kHz frame rate. Again, tor
some applications the frame rate could be increased to re-
duce this delay.
Typical Application
A typical application of these CODECs used in conjunction
with the TP3040 POM filter is shown below. The values of
resistor R1 and DC blocking capacitor C1, are norFcr'rtical.
The capacitor value should exceed 0.1 pF, R1 should be
less than 50 kft, and the product R1XC1 should exceed 4
RCV GAIN = 20 x log(
XMIT GAIN = 20 x log ('-1liti-ee) + 3dB
The power supply decoupling capacitors should be 0.1 pF.
In order to take advantage of the excellent noise perform-
ance of these CODECs, care must be taken in board layout
to prevent coupling of digital noise into the sensitive analog
lines. For card insertion into a hot connector, care should be
taken to insure that GNDA and GNDD are contacted prior to
q----------- PWM-
mgr] (i- W;
Vcc and V33.
R4 + R5
ix >o.t gr I
vmo --l R (l""'" MASTER cu:
vnl- Ct il, ma OUT ---.
ax IP 040 xurr SYNC ---
3 sum SSSLOG xun cut q------
PON wsns/ss
PWRO+ GNDD 3? GNDD tttN SYNC P,
PWRI Tf." RCY cu A-----
vrno erI ty" DIG M '_------.
tht pr
IOpFIjI
NOTE: 4, =ANALOG GROUND al., =DIGITAL GROUND
TL/H/6663-5
l'VQS lSdL/VQSl-Sdl/ I-‘VQL LSdllVQL lSdl
TP5116A/TP51 16A-1/TP5156A/TP5156A-1
Absolute Maximum Ratings
If MllltaryfAttroapams ttpetMed devlces are required, Voltage at Any Analog
please contact the National Semiconductor Sales Input or Output v- -0.3V to V+ + 0.3V
offlttefDhttrlttutors for avallablllty and speclllcations. Voltage at Any Digital
Operating Temperature - 25''C to + 125''C Input or Output GNDD- 0.3V to V+ + 0.3V
Storage Temperature -65t to + 150°C Lead Temperature
v+ with Respect to DIGITAL GROUND TV (Solderdip IO sec.) 300'C
v- with Respect to DIGITAL GROUND - 7v ESD rating to be determined.
DC Electrical Characteristics
Unless otherwise noted TA = 0°C to 70°C, V+ = 5.0V fc 5%, v- = -5.OV :5%. Typical characteristics are specified at V+
= 5.OV,V- = --5.ov and TA = 25''C. All digital signals are referenced to DIGITAL GROUND. All analog signals are referenced
to ANALOG GROUND. Limits printed in bold characters are guaranteed for v+ = 5.0V 1 5%, V- = -5.OV , 5%; TA = 0°C to
70'C by correlation with 100% electrical testing at TA = 25'C. All other limits are assured by correlation with other production
tests and/or product design and characterization.
Symbol Parameter J Condltlons Min Typ Max [ Units
DIGITAL INTERFACE
I. Input Current 0V
" Input Low Voltage 0.6 V
VIH Input High Voltage 2.2 V
VOL Output Low Voltage IOL = 3.2 mA 0.4 V
VOH Output High Voltage IOH = 6 mA 2.4 V
ANALOG INTERFACE
2. Analog Input Impedance Resistence in Series with 2 kn
when Sampling Approximately 70 pF
20 83:33: Impedance at Analog 10 20 n
lm Analog Input Bias Current VIN = 0V -0.1 0.1 0A
Rt M C1 DC Blocking Time Constant 4.0 ms
C1 DC Biocking Capacitor 0.1 pLF
RI Input Bias Resistor 50 kn
POWER DISSIPATION
ICC1 Operating Current, Vcc 3.5 tho mA
IBB1 Operating Current, V93 3.5 8.0 mA
AC Electrical Characteristics
Unless otherwise noted, TA = 25°C, V+ = 5.OV,V- = -5,0V. The analog input is a 0 dBmO, 1.02 kHz sine wave. The DIGITAL
INPUT is a PCM bit stream generated by passing a 0 dBmO, 1.02 kHz sine wave through an ideal encoder. All output levels are
sin x/x corrected, limits printed in bold characters are guaranteed for V+ = 5.0V i 5%, v- = -5.0V _+ 5%; TA = 0°C to 70°C
by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correlation with other production tests
and/or product design and characterization.
Symbol Parameter Conditions Min Typ Max Units
Absolute Level The nominal 0 dBmO levels for the
TP5116A is 1.227 Vrms and
1.231 Vrms for the TP5156A. The
resulting nominal overload level is
2.5V peak for all devices. All gain
measurements for the encode and
decode portions of the devices are
based on these nominal levels after
the necessary sin x/x corrections are
GRA Receive Gain, Absolute TA = 25°C, V + = 5V, V - = -5V
TP5116A, TP5156A -0Aatt 0.125 dB
TP5116A-1,TP5156A-1 --OATS OATS dB
GRAT Absolute Receive Gain TA = 0°C to 70°C
-0.05 0.05 dB
Variation with Temperature
AC Electrical Characteristics (Continued)
Unless otherwise noted, TA = 25''C, v+ 'c'= 5.0V, v- = -5.OV. The analog input is a 0 dBm0, 1.02 kHz sine wave. The
DIGITAL INPUT is a PCM bit stream generated by passing a 0 dBm0, 1.02 kHz sine wave through an ideal encoder. All output
levels are sin x/x corrected. Limits printed in bold characters are guaranteed for V+ = 5.0V i 5%, v-
0°C to 70"C by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correlation with other
production tests and/or product design and characterization.
-5.0V i5%;TA =
Symbol Parameter Conditions Min Typ Max Units
GRAV Absolute Receive Gain V+ = 5V i 5%, v- = - 5Vct: 5% _
Variation with Supply Voltage 0.07 0.07 dB
GXA Transmit Gain, Absolute TA = 25"C, V+ = 5V, v- = -5V
TP5116A,TP5156A -OA2t5 0.125 dB
TP5116A-1,TP5156A-1 ~0.175 0.175
GXAT Absolute Transmit Gain TA = 0°C to 7ty'C -
Variation with Temperature 0.05 0.05 dB
GXAV Absolute Transmit Gain V+ .-= 5V i5%, v- = -5V i5% -
Variation with Supply Voltage 0.07 th07 dB
GRAL Absolute Receive Gain CCITT Method 2 Relative to
Variation with Level - 10 dBmO
0 dBmO to 3 dBmO --o.a 0.3 dB
-40 dBmO to 0 dBmO -o.2 0.2 dB
-50 dBmO to -40 dBrnO -O.A 0.4 dB
-55 dBmo to -50 dBmO - 1.0 1.0 dB
GXAL Absolute Transmit Gain CCITT Method 2 Relative to
Variation with Level - 1O dBmO
0 dBmO to 3 dBmO -O.a 0.3 dB
- 40 dBmO to 0 dBmO - 0.2 0.2 dB
- 50 dBmO to -40 dBmO
TP5116A, TP5156A - 0.4 0.4 dB
TP5116A-1,TP5156A-1 -thqTS 0.475 dB
-55 dBmO to -50 dBmO - 1.0 1.0 dB
STDR Receive Signal to Distortion Sinusoidal Test Method Input
Ratio Level
-30 dBmO to 0 dBmo as dBC
- 4O dBmO " dBC
-45 dBmO " dBC
STDx Transmit Signal to Distortion Sinusoidal Test Method Input
Ratio Level
-30 dBmo toOdBmO as dBC
-40 dBmO " dBC
-45 dBmO " dBC
NR Receive Idle Channel Noise DR = Idle Code tt dBrnCO
Nx Transmit Idle Channel Noise TP5116A, VFx = ov " dBrnCO
TP5156A, l/Fx = 0V --tttt dBmOp
PPSRX Positive Power Supply Input Level = ov, VCC = 5.0 Voc so dB
Rejection, Transmit +300 mVrms, f = 1.02 kHz
PPSRR Positive Power Supply DR = Idle Code
Rejection, Receive Vcc = 5.0 VDC + 300 mVrms, 40 dB
f = 1.02 kHz
NPSRX Negative Power Supply Input Level = 0V, Vim = -5.0 V06 " dB
Rejection, Transmit +300 mVrms, f = 1.02 kHz
NPSRR Negative Power Supply Dn = Steady PCM Code,
Rejection, Receive VBB = -5.0 VDc + 300 mVrms, " dB
f = 1.02 kHz
CTXR Transmit to Receive Crosstalk DR ..-- Steady PGM Code --TS dB
CTRX Receive to TransmitCrosswalk Transmit Input Level = 0V
TP5116A --TO dB
TP5156A ~85 dB
(Note 2)
Note 1: Measured by extrapolation from the distortion test result at -50 dBmO level.
Note 2: Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law.
1 -207
l'VQS lSdl/VQSLSdl/l-‘VSI lSdl/VQL l-SdJ.
TP5116A/TP5116A-1/TP5156A/TP5156A-1
Timing Specifications Unless otherwise noted, TA = 0-0 to 70°C, v+ - +5v:5%, v- = -5v 1 5%. All
digital signals are referenced to DIGITAL GROUND and are measured at VIH and VIL as indicated in the Timing Waveforms.
Limits printed in bold characters are guaranteed for V+ == 5.0V 15%, v- = -5.0V A5%; TA = ty'G to 70'C by correlation
with 100% eiectrical testing at TA = 25'C. All other limits are assured by correlation with other production tests and/or product
design and characterization. All timing spetfmtmtitrns measured at VOH == 2.0V and VOL = 0.7V.
Symbol Parameter Conditions Min Typ Max Unlts
FM MASTER CLOCK Frequency 1.5 2.048 2.1 MHz
Fx, FR XMIT, RCV CLOCK Frequency 0.064 2.048 2.1 MHz
PWCLK Clock Pulse Width MASTER, XMIT, RCV CLOCKS 150 ns
tmy tFC Clock Rise and Fall Time MASTER, XMIT, RCV CLOCKS 50 ns
IRS, th Sync Pulse Rise and Fall Time RCV, XMIT, SYNC 50 ns
tRCS, txcs Clock to Sync Delay RCV, XMIT 0 ns
txss XMIT SYNC Set-Up Time 150 ns
tXDD XMIT Data Delay Load = 100 pF + 2 LSTTL Loads 200 ns
tXDp XMIT Data Present Load == 100 pF + 2 LSTTL Loads 200 ns
tXDT XMIT Data TRI-STATE' 150 ns
tsnc RCV CLOCK to RCV SYNC Delay 0 ns
tags RCV Data Set-Up Time 0 ns
tRSS RCV SYNC Set-Up Time 150 ns
tRDH RCV Data Hold Time 100 ns
1XSL XMIT SYNC Low Time 64 kHz Operation 300 ns
tRSL RCV SYNC Low Time 64 kHz Operation 17 (Note 3)
Nata 3: RCV SYNC must remain low for at least 17 cycles of MASTER CLOCK, each trams.
Timing Waveforms
72 RN: or Greater Operation
SYNC J
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mg l 2 s 4 ' c , s
tets km." _ "cu tecs ‘sac
gri-lsj:t" “T '1' ft JE,-,-,---
‘m tlit s 4ksIerrrs2fIIfillllll)
TL/H/6663-3
64 kHz Operation
am 1 2 s 4 5 o 1 a s
sx,'fl ll uv .m
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TLlH/8663-4
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
TP5156AJ - product/tp5156aj?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nuIl-wwe
TP5156A-1 - product/tp5156a-1?HQS=Tl-null-nu|I-dscataIog-df-pf-null-wwe
TP5116AJ - product/tp5116a]?HQS=T|—nuIl-nu|I-dscatalog-df-pf-nu||-wwe
TP5116A-1 - product/tp5116a-1?HQS=T|—null-nu|I-dscataIog-df-pf-nuII-wwe
