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TMS320DM6467TZUT1-TMS320DM6467TZUT9 Fast Delivery,Good Price
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TMS320DM6467TZUT1TIN/a1200avaiDigital Media System-on-Chip 529-FCBGA 0 to 85
TMS320DM6467TZUT9TEXASN/a275avaiDigital Media System-on-Chip 529-FCBGA 0 to 85


TMS320DM6467TZUT1 ,Digital Media System-on-Chip 529-FCBGA 0 to 85• External Memory Interfaces (EMIFs) – SIR and MIR (0.576 MBAUD)– Up to 400-MHz 32-Bit DDR2 SDRAM M ..
TMS320DM6467TZUT9 ,Digital Media System-on-Chip 529-FCBGA 0 to 85 SPRS605C –JULY 2009–REVISED JUNE 20121.2 DescriptionThe TMS320DM6467T (also referenced as DM6467T) ..
TMS320DM6467ZUT7 ,Digital Media System-on-Chip 529-FCBGA 0 to 85 SPRS403H –DECEMBER 2007–REVISED JUNE 20121.2 DescriptionThe TMS320DM6467 (also referenced as DM646 ..
TMS320DM648ZUT7 ,Digital Media Processor 529-FCBGA 0 to 90 SPRS372H –MAY 2007–REVISED APRIL 2012ports (DM648) or one SGMII port (only DM647); a 4-bit transmi ..
TMS320DM648ZUT9 ,Digital Media Processor 529-FCBGA 0 to 90• VLYNQ™ Interface (FPGA Interface) (Multiplexed With Other Device Functions)• On-Chip ROM Bootload ..
TMS320DM648ZUTD9 ,Digital Media Processor 529-FCBGA -40 to 90Features1• High-Performance Digital Media Processor • C64x+ L1/L2 Memory Architecture– 720-MHz, 800 ..
TPS54313PWP ,Low Input Voltage 3A Synchronous Buck Converter with 1.5V Output SLVS416C–FEBRUARY 2002–REVISED JANUARY 20155 Pin Configuration and FunctionsPWP Package20-Pin HTSS ..
TPS54313PWPG4 ,3V to 6V Input, 3A Synchronous Step-Down SWIFT? Converter with 1.5V Output 20-HTSSOP -40 to 125features area true, high performance, voltage error amplifier that• Fast Transient Responseprovides ..
TPS54313PWPR ,Low Input Voltage 3A Synchronous Buck Converter with 1.5V OutputBlock Diagram..... 912 Mechanical, Packaging, and Orderable7.3 Feature Description...... 9Informati ..
TPS54314 ,Low Input Voltage 3A Continuous Buck Converter with 1.8V Outputfeatures area true, high performance, voltage error amplifier that• Fast Transient Responseprovides ..
TPS54314PWP ,Q1 SLVS416C–FEBRUARY 2002–REVISED JANUARY 20155 Pin Configuration and FunctionsPWP Package20-Pin HTSS ..
TPS54314PWPRG4 ,Q1Block Diagram..... 912 Mechanical, Packaging, and Orderable7.3 Feature Description...... 9Informati ..


TMS320DM6467TZUT1-TMS320DM6467TZUT9
Digital Media System-on-Chip
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
TMS320DM6467T
Digital Media System-on-Chip
Checkfor Samples: TMS320DM6467T Digital Media System-on-Chip (DMSoC)
1.1 Features 128K-Byte L2 Unified Mapped RAM/Cache• High-Performance Digital Media SoC (Flexible RAM/Cache Allocation)– 1-GHz C64x+™ Clock Rate • ARM926EJ-S Core– 500-MHz ARM926EJ-S™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb®– Eight 32-Bit C64x+ Instructions/Cycle Mode) Instruction Sets– 8000 C64x+ MIPS – DSP Instruction Extensions and Single Cycle– Fully Software-Compatible With C64x/ MACARM9™ – ARM® Jazelle® Technology– Industrial Temperature Devices Available – EmbeddedICE-RT™ Logic for Real-Time• Advanced Very-Long-Instruction-Word (VLIW) DebugTMS320C64x+™ DSP Core • ARM9 Memory Architecture– Eight Highly Independent Functional Units – 16K-Byte Instruction Cache• Six ALUs (32-/40-Bit), Each Supports – 8K-Byte Data CacheSingle 32-Bit, Dual 16-Bit,or Quad 8-Bit – 32K-Byte RAMArithmetic per Clock Cycle 8K-Byte ROM• Two Multipliers Support Four16x 16-Bit
Multiplies (32-Bit Results) per Clock • Embedded Trace Buffer™ (ETB11™) With 4KB
Cycleor Eight8x 8-Bit Multiplies (16-Bit Memory for ARM9 Debug
Results) per Clock Cycle • Endianness: Little Endian for ARM and DSP Load-Store Architecture With Non-Aligned • Dual Programmable High-Definition VideoSupport Image Co-Processor (HDVICP) Engines 64 32-Bit General-Purpose Registers – Supportsa Rangeof Encode, Decode, and Instruction Packing Reduces Code Size Transcode Operations All Instructions Conditional • H.264, MPEG2, VC1, MPEG4 SP/ASP Additional C64x+™ Enhancements • 150-MHz Video Port Interface (VPIF) Protected Mode Operation – Two 8-Bit SD (BT.656), Single 16-Bit HD
(BT.1120),or Single Raw (8-/10-/12-Bit) Video for Error Detection Capture Channels Two 8-Bit SD (BT.656)or Single 16-Bit HD Loop
(BT.1120) Video Display Channels Engine (VDCE) Vertical Downscaling Chroma Conversion Two Transport (One Parallel/Serial One Serial– Normalization, TSIF for MPEG Transport Stream – Simultaneous Synchronousor Complex Asynchronous Input/Output Streams – Absolute Time – PID Filter With7 PID Filter Tables (Direct – Clock Reference Generator (CRGEN) Modules for System Time-Clock
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