TMS320DM6441ZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA Features12• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture– C64x+™ DSP Clock ..
TMS320DM6443AZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA Features12• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture– 594-MHz C64x+™ Cl ..
TMS320DM6443ZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA SPRS282G–DECEMBER 2005–REVISED AUGUST 20101.2 DescriptionThe TMS320DM6443 (also referenced as DM64 ..
TMS320DM6443ZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA • External Memory Interfaces (EMIFs) • 10/100 Mb/s Ethernet MAC (EMAC)– 32-Bit DDR2 SDRAM Memory Co ..
TMS320DM6446AZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA 0 to 85 SPRS283H–DECEMBER 2005–REVISED SEPTEMBER 2010TMS320DM6446Digital Media System-on-ChipCheck for Sam ..
TMS320DM6446AZWTA ,DaVinci Digital Media System-on-Chip 361-NFBGA -40 to 105FeaturesProcessing– Byte-Addressable (8-/16-/32-/64-Bit Data)• Glueless Interface to Common Video– ..
TPS54310PWPG4 ,Q1Maximum Ratings.. 411.1 Layout Guidelines.... 187.2 ESD Ratings........ 411.2 Layout Example....... ..
TPS54310PWPR ,Q1Features... 18.3 Feature Description.... 102 Applications..... 18.4 Device Functional Modes.... 123 ..
TPS54310PWPRG4 ,3V to 6V Input, 3A Synchronous Step-Down SWIFT? Converter 20-HTSSOP -40 to 125features are a true,• Externally Compensated for Design Flexibility high performance, voltage error ..
TPS54310QPWPRQ1 ,Q1 TPS54310-Q1SGLS280D − JANUARY 2005 − REVISED JUNE 2009RECOMMENDED OPERATING CONDITIONSMIN NOM MAX ..
TPS54310QPWPRQ1 ,Q1features are a true, high-performance,1% Accuracyvoltage error amplifier that provides high perform ..
TPS54311PWP ,Low Input Voltage 3A Synchronous Buck Converter with 0.9V Output SLVS416C–FEBRUARY 2002–REVISED JANUARY 20155 Pin Configuration and FunctionsPWP Package20-Pin HTSS ..
TMS320DM6441AZWT-TMS320DM6441ZWT
DaVinci Digital Media System-on-Chip
TMS320DM6441
www.ti.com SPRS359E–SEPTEMBER 2006–REVISED AUGUST 2010
TMS320DM6441
Digital Media System-on-Chip
Checkfor Samples: TMS320DM6441 Digital Media System-on-Chip (DMSoC)
1.1 Features High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture C64x+™ DSP Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct
Mapped)• 405-MHz (Max)at 1.05Vor 513-MHz (Max) 1.2V – 80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)– ARM926EJ-S™ Clock Rate 64K-ByteL2 Unified Mapped RAM/Cache• 202.5-MHz (Max)at 1.05Vor 256-MHz (Flexible RAM/Cache Allocation)(Max)at 1.2V ARM926EJ-S Core– Eight 32-Bit C64x+ Instructions/Cycle Support for 32-Bit and 16-Bit (Thumb®– 4752 C64x+ MIPS Mode) Instruction Sets– Fully Software-Compatible With C64x/ – DSP Instruction Extensions and Single CycleARM9™ MAC• Advanced Very-Long-Instruction-Word (VLIW) ARM® Jazelle® TechnologyTMS320C64x+™ DSP Core Embedded ICE-RT™ Logic for Real-Time– Eight Highly Independent Functional Units Debug• Six ALUs (32-/40-Bit), Each Supports • ARM9 Memory ArchitectureSingle 32-Bit, Dual 16-Bit,or Quad 8-Bit
Arithmetic per Clock Cycle – 16K-Byte Instruction Cache Two Multipliers Support Four16x 16-Bit – 8K-Byte Data Cache
Multiplies (32-Bit Results) per Clock – 16K-Byte RAMCycleor Eight8x 8-Bit Multiplies (16-Bit – 8K-Byte ROMResults) per Clock Cycle • Embedded Trace Buffer™ (ETB11™) With 4KB– Load-Store Architecture With Non-Aligned Memory for ARM9 DebugSupport • Endianness: Little Endian for ARM and DSP– 64 32-Bit General-Purpose Registers • Video Imaging Co-Processor (VICP)– Instruction Packing Reduces Code Size • Video Processing Subsystem – Front End Provides: • CCD and CMOS Imager Interface Operation • BT.601/BT.656 Digital YCbCr 4:2:2 for Error Detection (8-/16-Bit) Interface for Real-Time Image • Glueless Video Decoders– Byte-Addressable Data) • Histogram Module • Auto-Exposure, Auto-White Auto-Focus Module • Resize – Resize 1/4xto 4x Complex – Separate Horizontal/Vertical Control
