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TLE6236G
Smart Low Side Switches
Datasheet TLE 6236 G
Smart Octal Low-Side Switch
Features Product SummaryShort Circuit Protection
• Overtemperature Protection
• Overvoltage Protection8 bit Serial Data Input and Diagnostic
Output (acc. SPI protocol)Direct Parallel Control of Four Chan-
nels for PWM ApplicationsGeneral Fault FlagDaisy chainable with other SPI devicesVery Low Leakage Current (≤ 1µA)Compatible with 3V Micro Controllers
Electostatic Discharge (ESD) Protection ApplicationµC Compatible Power Switch for 12V and 24VApplicationsSwitch for Automotive and Industrial SystemSolenoids, Relays, Resistive Loads, LEDs
• Robotic Controls
General descriptionOctal Low-Side Switch in Smart Power Technology (SPT) with a
Serial
Peripheral Interface (SPI) and eight open drain DMOS output stages. The TLE 6236 G is protected byembedded protection functions and designed for automotive and industrial applications. The outputstages are controlled via an SPI Interface. Additionally four channels can be controlled direct in parallel
for PWM applications. The open load detection (pull down sources) can be disabled via the OL/PRG
pin. Then the leakage current is reduced to 1µA (max.) to avoid e.g. the glowing of LEDs in off state.
Therefore the TLE 6236 G is particularly suitable for body control units, dash board illumination or en-gine management systems.
Block Diagram
Datasheet TLE 6236 G
Detailed Block Diagram
Datasheet TLE 6236 G
Pin Description
Pin Configuration (Top view)GNDGNDNC
OUT126OUT8
OUT225OUT7
IN124RESETIN223SI22SCLK
OL/PRGSO
IN320FAULT
IN419CS
OUT318OUT6
OUT417OUT516NC
GND15GND
P-DSO 28
Datasheet TLE 6236 G
Maximum Ratings for Tj = – 40°C to 150°C Datasheet TLE 6236 G
Electrical CharacteristicsVS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
1. Power SupplyV3
2. Power Outputs
3. Digital Inputs
4. Digital Outputs (SO, FAULT)
5. Diagnostic Functions Datasheet TLE 6236 G
Electrical Characteristics cont.
6. SPI-Timing
Datasheet TLE 6236 G
Functional DescriptionThe TLE 6236 G is an octal-low-side power switch which provides a serial peripheral interface
(SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power tran-
sistors are protected against short to VBB, overload, overtemperature and against overvoltage
by an active zener clamp.The diagnostic logic recognizes a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Output Stage ControlEach output is independently controlled by an output latch and a common reset line, which
disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A
logic high input data bit turns the respective output channel ON, a logic low data bit turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output buffer.
Special conditions for Channel 1 to 4:In addition to the serial control of the outputs it is possible to control channel 1 to channel 4
directly in parallel for PWM applications. These inputs are high active and ORed with the SPI
control bit. The parallel inputs are provided with internal pull down sources, to guarantee thatthe channels are switched off when the inputs are not connected.
The table shows the OR-operation of the parallel inputs 1 ..4 and the corresponding SPI bits.
The outputs 5 .. 8 can be controlled in serial via SPI
Interface
Serial Control Bits (SI)MSB LSB
Serial Diagnostic Bits (SO)MSB LSB
Datasheet TLE 6236 G
Power Transistor Protection Functions1)Each of the eight output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 500 mA. The continuous current for each channel is
200 mA (all channels ON).
Each output is protected by embedded protection functions. In the event of an overload orshort to supply, the current is internally limited and a fault bit is generated for each output indi-
vidually (early warning). If this operation leads to an overtemperature condition, a second
protection level (about 170 °C) will change the output into a low duty cycle PWM (channel se-
lective thermal shutdown with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6236 G by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition:-diagnostic status information is transferred from the
power
outputs into the shift register.serial input data can be clocked in from then on- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS Low to High transition: -transfer of SI bits from shift register into output buffers - reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
The device will react to the CS
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6236 G.The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while
the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of
serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.A logic high bit at this pin (within the data byte) will switch the corresponding output on.
