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TLE6232GP-TLE6232GP.-TLE6232GP..
Smart Low Side Switches
Data Sheet TLE 6232 GP Smart Six Channel Low-Side Switch Features Product Summary Short Circuit Protection up to 24 V
• Over-temperature Protection
• Over-voltage Protection 16 bit Serial Data Input and Diagnostic Output (2 bit/ch. acc. SPI protocol) Direct Parallel Control of all six Chan-
nels for PWM Applications General Fault Flag Low Quiescent Current Compatible with 3V Micro Controllers
Electrostatic Discharge (ESD) Protection Parallel Inputs High or Low Active Programmable
Application µC Compatible Power Switch for 12 V and 24V Applications Switch for Automotive and Industrial System Solenoids, Relays and Resistive Loads
• Robotic Controls
General description Six Channel Low-Side Switch in Smart Power Technology (SPT) with a
Serial Peripheral Interface (SPI) and six open drain DMOS output stages. The TLE 6232 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via
an SPI Interface. Additionally all six channels can be controlled direct in parallel for PWM applications.
Therefore the TLE 6232 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
Detailed Block Diagram
RESETFAULT
SCLK
IN1
OUT6
PRG
IN6
Data Sheet TLE 6232 GP FAULTRESET
SCLK
IN1
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
PRG
GND
IN3
IN4
IN2
IN5
IN6
Data Sheet TLE 6232 GP Pin Description Pin Configuration (Top view) GND GND
NC NC
OUT5 NC
NC NC
OUT1 OUT4
IN5 NC
IN1 IN4
VS SI
RESETSCLK
CS SO
PRG FAULT
IN2 IN3
IN6 NC
OUT2 OUT3
NC NC
OUT6 NC
NC NC
GND GND Power SO 36
Heat Slug internally connected to ground pins
Data Sheet TLE 6232 GP Maximum Ratings for Tj = – 40°C to 150°C Data Sheet TLE 6232 GP Electrical Characteristics
1. Power Supply, Reset
2. Power Outputs
3. Digital Inputs
4. Digital Outputs (SO, FAULT) Data Sheet TLE 6232 GP Electrical Characteristics cont.
5. Diagnostic Functions
6. SPI-Timing 3 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
Data Sheet TLE 6232 GP Description of the Power Stages 4 low side power switches for nominal currents up to 3A (power stages OUT1 to OUT4). Con-
trol is possible by input pins or via SPI. For TJ = 150°C the on-resistance of the power
switches is below 500mΩ.
2 low side power switches for nominal currents up to 1.5A (power stages OUT5 and OUT6).
Control is possible by input pins or via SPI. For TJ = 150°C the on-resistance of the power
switches is below 1Ω.
In order to increase the switching current or to reduce the power dissipation parallel connec-
tion of power stages is possible.
Each of the 6 output stages is equipped with its own zener clamp, which limits the output volt-age to a maximum of 60V. The outputs are provided with a current limitation set to a minimum
of 1.5A resp. 3A. Each power stage is equipped with an own temperature sensor.
Each output is protected by embedded protection functions5). In case of overload or short-
circuit to UBatt the current is internally limited and the corresponding bit combination is set (early warning). If this operation leads to an over-temperature condition, a second protection
level (about 170°C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
The following faults can be detected (individually for each output):
- short to UBatt: (SCB/overload) can be detected when switches are On state
- short to ground: (SCG) can be detected when switches are Off state
- open load: (OL) can be detected when switches are Off state
- over-temperature: (OT) will only be detected when switches are On state
The fault conditions SCB, SCG and OL will not be stored until an integrated filtering time is
expired (please note for PWM application). If, at one output, several errors occur in a se-
quence, always the last detected error will be stored (with filtering time). All fault conditions are
encoded in two bits per switch and are stored in the corresponding SPI registers. Additionally there are two central diagnostic bits: one especially for over-temperature (latched result of an
OR-operation out of the 6 signals of the temperature sensor) and one for fault occurrence at
any output. A fault that has been detected and stored in the fault register must not be replaced
by o.k.-state (11) unless it is read out by the RD_DIAG command sent by the microcontroller
or an internal or external reset has been applied. I.e. the fault register will be cleared only by the RD_DIAG command.
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 6 are high active PRG = Low (GND): Parallel inputs Channel 1 to 6 are low active.
If the parallel input pins are not connected (independent of high or low activity), channels 1 to
6 are switched OFF.
PRG pin itself is internally pulled down when it is not connected.
Data Sheet TLE 6232 GP The effect of the integrated under-voltage detection is similar to the effect of an external reset
at pin Reset (except low current consumption):
- locks all power switches regardless of their input signals
- clears the fault registers - resets SPI control register
Parallel Connection of Power Stages The power stages which are connected in parallel have to be switched on and off simultane-
ously.
In case of overload the ground current and the power dissipation are increasing. The applica-
tion has to take into account that all maximum ratings are observed (e.g. operating tempera-
ture TJ and total ground current IGND, see Maximal Ratings).
The maximum current limitation value (or overload detection threshold) of the parallel con-nected power stages is the summation of the corresponding maximum values of the power
stages (IOUT(lim)x + IOUT(lim)y + ....).
Note 1: Power stages of the same type have the same nominal current
Note 2: Only for 3A power stages
Note 3: Parallel connection of power stage type 3A/53V with type 1.5A/53V
SPI Interface The serial SPI interface makes possible communication between TLE6232 and the microcon-
troller. TLE 6232 GP always works in slave mode whereas the microcontroller provides the master
function. The maximum baud rate is 5MBaud.
Applying a chip select signal at CS and setting bit 7 and bit 6 of the instruction byte to „1“ and
„0“ TLE 6232 GP is selected by the SPI master. SI is the data input (Signal In), SO the data
output (Signal Out). Via SCLK (Serial Clock Input) the SPI clock is given by the master.
Data Sheet TLE 6232 GP SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6232 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - SO changes from high impedance state to logic high or low state corresponding to the SO bits CS Low to High transition: - transfer of SI bits from shift register into output buffers - reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6232 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition. The number of clock pulses will be counted during a
chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were
counted during CS is active.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-
agnostics section). The data byte contains the input information for the six channels. A logic high level at this pin (within the data byte) will switch on the power switch, provided that the
corresponding parallel input is also switched on (AND-operation for channel 1 to 6).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing
from1“ and „0“ the data output SO remains into tri-state.
Data Sheet TLE 6232 GP SPI Interface
SPI Communication A SPI communication starts with a SPI instruction (SI control word) sent from the controller to
TLE 6232 GP. Simultaneously the device sends the first SO byte back to the µC.
During a writing cycle the controller sends the data after the SPI instruction, beginning with the
MSB. During a reading cycle, after having received the SPI instruction, TLE 6232 GP sends
the corresponding data to the controller, also starting with the MSB.
The SPI Interface consists of three register:
