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TLC556MTIBBN/a639avaiLow-Power Dual LinCMOS<TM> Timer
TLC556MDRTIBBN/a639avaiLow-Power Dual LinCMOS<TM> Timer
TLC556MDRG4TIN/a2530avaiLow-Power Dual LinCMOS<TM> Timer 14-SOIC


TLC556MDRG4 ,Low-Power Dual LinCMOS<TM> Timer 14-SOIC electrical characteristics.functional
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TLC556M-TLC556MDR-TLC556MDRG4
Low-Power Dual LinCMOS<TM> Timer
High Output-Current Capability Sink 100 mA Typ
Source 10 mA Typ
Output Fully Compatible With CMOS, TTL,
and MOS
Low Supply Current Reduces Spikes
During Output Transitions
Single-Supply Operation From 2 V to 15 V Functionally interchangeable With the
NE556; Has Same Pinout


description

The TLC556 series are monolithic timing circuits
fabricated using the TI LinCMOS process, which
provides full compatibility with CMOS, TTL, and
MOS logic and operates at frequencies up to MHz. Accurate time delays and oscillations are
possible with smaller, less-expensive timing
capacitors than the NE556 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
Like the NE556, the TLC556 has a trigger level
approximately one-third of the supply voltage and
a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control
voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high.
If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is
reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing
cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures
at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in
handling these devices, as exposure to ESD may result in degradation of the device parametric performance.
All unused inputs should be tied to an appropriate logic level to prevent false triggering.
The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from
–40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of –55°C
to 125°C.
1 CONT
1 RESET
1 OUT
1 TRIG
GND
2 THRES
2 CONT
2 RESET
2 OUT
2 TRIG
2 THRES
2 CONT
2 RESET
1 CONT
1 RESET
1 OUT
FK PACKAGE
(TOP VIEW)

1 THRES1 DISCHNC
2 TRIG
2 OUT2 DISCH
1 TRIG
GND
NC–No internal connection
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