TLC552CN ,Dual LinCMOS(TM) Timermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TLC5540CNSR ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Powermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TLC5540INSR ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Powerblock diagramResistorReferenceOEDividerREFB270 ΩNOMLower SamplingREFTLower EncoderD1(LSB)Comparator ..
TLC5540INSRG4 ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Power 24-SO -40 to 85SLAS105D − JANUARY 1995 − REVISED APRIL 2004Terminal FunctionsTERMINALI/O I/O DESCRIPTION DESCRIPTI ..
TLC5540IPW ,8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Powerfeatures(TOP VIEW) 8-Bit Resolution Differential Linearity ErrorOE DGND1 24− ±0.3 LSB Typ, ±1 LS ..
TLC555CD ,Low Power TimerFeatures 3 DescriptionThe TLC555 is a monolithic timing circuit fabricated1• Very Low Power Consump ..
TMP47C452AN , CMOS 4-BIT MICROCONTROLLER
TMP47C452AN , CMOS 4-BIT MICROCONTROLLER
TMP47C620F , CMOS 4-BIT MICROCONTROLLER
TMP47C670N , CMOS 4-BIT MICROCONTROLLER
TMP47C858F , CMOS 4-BIT MICROCONTROLLER
TMP47C860N , CMOS 4-BIT MICROCONTROLLER
TLC552CN
Dual LinCMOS(TM) Timer
High Output-Current CapabilitySink 100 mA Typ
Source 10 mA Typ Output Fully Compatible With CMOS, TTL,
and MOS Low Supply Current Reduces Spikes
During Output Transitions High-Impedance Inputs ...1012 W Typ Single-Supply Operation From 1 V to 18 V Functionally Interchangeable With the
NE556; Has Same Pinout
descriptionThe TLC552 is a dual monolithic timing circuit
fabricated using TI LinCMOS process, which
provides full compatibility with CMOS, TTL, and
MOS logic and operation at frequencies up to
2 MHz. Accurate time delays and oscillations are
possible with smaller, less-expensive timing
capacitors than the NE555 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
Like the NE556, the TLC552 has a trigger level
approximately one-third of the supply voltage and
a threshold level approximately two-thirds of the
supply voltage. These levels can be altered by use
of the control voltage terminal. When the trigger
input falls below the trigger level, the flip-flop is set
and the output goes high. If the trigger input is
above the trigger level and the threshold input is
above the threshold level, the flip-flop is reset and
the output is low. The reset input can override all other inputs and can be used to initiate a new
timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC552 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
LinCMOS is a trademark of .
RESET
OUT
TRIG
GND
CONT
RESET
OUT
TRIG
TIMER
# 2
# 1
functional block diagram (each timer)RESET can override TRIG and THRES.
TRIG can override THRES.
AVAILABLE OPTIONS
THRES
VDD
TRIG
GND
RESET
OUT
DSCHThe D packages are available taped and reeled. Add the suffix R
to the device type when ordering (i.e., TLC552CDR).
