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TH58V128FTTOSHIBAN/a108avai128Mbit (16M x 8bit) CMOS NAND E2PROM


TH58V128FT ,128Mbit (16M x 8bit) CMOS NAND E2PROMTH58V128FT128 Mbit (16M M 8bit) CMOS NAND EZPROMThe TH58V128 device is a single 3.3 volt 128M (138, ..
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TH58V128FT
128Mbit (16M x 8bit) CMOS NAND E2PROM
TOSHIBA TH58V128FT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128 Mbit (16M x 8bit) CMOS NAND EZPROM
DESCRIPTION
The TH58V128 device is a single 3.3 volt 128M (138,412,032) bit NAND Electrically Erasable and
Programmable Read Only Memory (NAND EEPROM) organized as 528 bytes M 32 pages X 1024 blocks.
The device has a 528 byte static register which allows the rogram and read data to be transferred
between the register and the memory cell array in 528 yte increments. The erase operation is
implemented in a single block unit (16K bytes + 512 bytes : 528 bytes M 32 pages).
The TH58V128 is a serial type of memory device which utilizes the I/O pins for both address and
datainput/ output as well as command inputs. The erase and Erogram gperations are automatically
executed making the device most suitable for applications sue as Soli State File Stora e, Voice
Recording, Image File Memory for digital still cameras and other systems which require a hid -density
non-volatile memory data storage.
FEATURES
0 Organization 0 Power supply
Memory cell array 528 M 16K M 8X 2 Vcc = 3.3 V l 0.3 V
Register 528 M 8 0 Access time
Page size 528 bytes Cell array- Register 7 ps max
Block size (16K + 512) bytes Serial Read Cycle 50 ns min
0 Mod 0 Operating current
Read Read (80ns cycle) 10mA typ
Reset, Auto page program Program (ave.) 10mA typ
Auto block erase, Status read Erase (ave.) 10mA typ
0 Mode control Standby (CMOS) 100 PA max
Serial ingut/output 0 Package
Comman control TH58V128FT ..TSOPlI44/40-P-400-0.80J
(Weight : 0.51g typ)
PIN ASSIGNMENT (TOP VIEW)
TH58V128FT PIN NAMES
..... ywif1442|v -
ite C 2 43 3?? ttoss " port
ALE I: 3 42 CIM CE Chip enable
M I: 4 41 Cl R/B . W Write enable
....WRJZ. .5 ............ 40..C..l..ty.t.....i -
NC I: 6 39 Cl NC RE Read enable
NC l: 7 38 EINC CLE Command latch enable
'di E 3 17, Cl le l Address latch enable
NC I: 10 35 Cl NC WP Write protect
11 34 R/iT Ready/ Busy
12 33 ' '
NC E 13 32 Cl NC OP Option Pin
NC I: 14 31 Cl NC Vcc Power supply
NC I: 15 30 Cl NC
NC I: 16 29 Cl NC Vccq Output Buffer Power supply
....N.c..E. .1..7. .......... 2.8..:_l.N.c. ..... Vss Ground
I/O1 E18 27 ZII/oaE
g l/O2 E 19 26 Cl l/O? i' OP: GNDInput : 528Byte/page Operation
g l/O3 E 20 25 Cl l/O6 i' VCC Input :512Byte/Page Operation
il/O4 E21 24ZII/oss
. .... yss..r. .2..2. .......... .2..3..p.)./cc9..::.
980910EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to the foreign exchange and foreign trade laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-11-09 1/32
BLOCK DIAGRAM
Vccq Vcc GND
i [irzzzz1status-r'miste" i i
I/O1o<:-F i.' " ( 4 Address register _ Column buffer
to i i." Control q" g r? Column decoder
I/O 8tyA:-e ctrcutt _ Command register I g Data register
A I 7. Sense amp A-
E o-r , B i
W f R d i
CLE o-r a f o e E
ALE CY-F Logic = antrpl g f , f, i' Memory
W ." control circuit g g g , i.' cell array
RE o-r s f, g E
W o-v g I :
HV generator I I
FIR/Vi-SF-
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
Vcc Power supply Voltage - 0.6 to 4.6 V
Vccq output Buffer Power Supply - 0.6 to 6.0 V
VIN Input Voltage - 0.6 to 6.0 V
Vvo Input /Output Voltage - 0.6V _ Vccq + 0.3V(S 6.0V) V
PD Power Dissipation 0.3 W
TSTG Storage Temperature - 55 to 150 'C
TSOLDER Sold ering Temperature(10s) 260 ''C
TOPR Operating Temperature Oto 70 "C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
ClN Input " = 0V - 20 "
COUT Output VOUT = 0V - 20 "
* This parameter is periodically sampled and is not tested for every component.
1998-11-09 2/32
TOSHIBA TH58V128FT
VALID BLOCKS *
SYMBOL PARAMETER MIN TYP MAX UNIT
NVB Valid Block Number 1004 1016 1024 Blocks
* The TH58V128 occasionally contains unusable blocks. Refer to Application Note (14)
toward the end of this document.
DC RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP MAX UNIT
Vcc Power Supply Voltage 3.0 3.3 3.6 V
Vccq Output Buffer Power Supply 3.0 - 5.5 V
" High Level Input Voltage 2.0 - Vccq + 0.3 *1 V
" Low Level Input Voltage - 0.3 *2 - 0.8 V
*1: OP:Vcc+0.3V
*2: - 2V (pulse width E 20 ns)
DC CHARACTERISTICS
(Ta = ty' to 70 'T, Vcc = 3.3 V i 0.3 V ' Vccq = 3.0V to 5.5V)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VIN = 0V to Vccq - - i 10 PA
Lo Output Leakage Current VouT = 0.4V to Vccq - - + 10 ,uA
lcco1 Operating Current (Serial Read) E = VIL, Iout = 0 mA, tcycle = 50 ns - 10 30 mA
Icco3 Operating Current (Command Input) tcycle = 50 ns - 10 30 mA
Iccoo Operating Current (Data Input) tcyde = 50 ns - 10 30 mA
lccos Operating Current (Address Input) tcyde = 50 ns - 10 30 mA
lcco7 Programming Current - - 1O 30 mA
lccog Erasing Current - - 10 30 mA
Iccsl Standby Current(TTL) E = VIH - - 1 mA
Iccs2 Standby Current(CMOS) E = Vccq - 0.2V - - 100 ,uA
VOH High Level Output Voltage IOH = - 400 PA 2.4 - - V
VOL Low Level Output Voltage kw = 2.1 mA - - 0.4 V
IOL(R/§) Output Current of (R/E) Pin VOL = 0.4V - 8 - mA
1998-11-09 3/32
TOSHIBA TH58V128FT
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = ty' to 70 °C, Vcc = 3.3V i 0.3V ' Vccq = 3.0 V to 5.5 V)
SYMBOL PARAMETER MIN MAX UNIT NOTE
tCLs CLE Set-Up Time 0 - ns
tcLH CLE Hold Time 10 - ns
tcs E Set-Up Time 0 - ns
tCH E Hold Time 10 - ns
twp Write Pulse Width 25 - ns
tALs ALE Set-Up Time 0 - ns
tALH ALE Hold Time 10 - ns
tos Data Set-Up Time 20 - ns
tDH Data Hold Time 10 - ns
twc Write Cycle Time 50 - ns
tWH W High Hold Time 15 - ns
tww W High to m Low 100 - ns
tRR Ready to E Falling Edge 20 - ns
tRp Read Pulse Width 35 - ns
tRC Read Cycle Time 50 - ns
tREA E Access Time (Serial Data Access) - 35 ns
tcEH E High Time for interruption of data transfer from cell to register 100 - ns (2)
tREAID E Access Time (ID Read) - 35 ns
tOH Data Output Hold Time 10 - ns
tRHZ E High to Output High Impedance - 30 ns
tcHz E High to Output High Impedance - 20 ns
tREH E High Hold Time 15 - ns
th Output High Impedance to E Rising Edge 0 - ns
tRSTO E Access Time (Status Read) - 35 ns
tcho E Access Time (Status Read) - 45 ns
tRHW E High to W Low 0 - ns
tWHC m High to E Low 30 - ns
tWHR m High to E Low 30 - ns
tAm ALE Low to E Low (ID Read) 100 - ns
tCR E Low to E Low (ID Read) 100 - ns
tR Data transfer from memory cell array to data register - 7 ps
twa W High to Busy - 100 ns
tAR2 ALE Low to E Low (Read Cycle) 50 - ns
in E Last Clock Rising Edge to Busy (in Sequential Read) - 100 ns
tCRY E High to Ready (at interruption of data transfer from cell to register) - 50+tr(R/§) ns (1)(2)
tRST Device Resetting Time (Read/Program/Erase) - 6/10/500 M;
AC TEST CONDITIONS
Input level : 2.4 V/ 0.4 V
Input pulse rise and fall time : 3ns
Input comparison level : 1.5 V/ 1.5 V
Output data comparison level : 1.5V/1.5 V
Output load : lTTL & CL (100 pF)
1998-11-09 4/32
TOSHIBA TH58V128FT
Note : (1) CE High to Ready time depends on the pull-up resistor tied to the MT pin.
(Refer to Application Note (7) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns.
If the "rlTif to UE delay is less than 30ns, MT signal stays Ready.
tCEH 2 100 ns
* *VIH or VIL
E / Eh
E I I I I I i
Ci) Ci? : 0 to 30 ns -9 Busy signal is not output.
525 526 527 /
R / E lil j
tCRY ’
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0° to 70 "C, Vcc = 3.3V i 0.3V ' Vccq = 3.0 V to 5.5 V)
SYMBOL PARAMETER MIN TYP MAX UNIT NOTE
tPROG Average Programming Time 200 1000 ps
N Number of Programming Cycles on Same Page 10 (1)
tBERASE Block Erasing Time 2 20 ms
P/E Number of Program/Erase Cycles 1x 106 (2)
(1) Refer to Application Note (12) toward the end of this document.
(2) Refer to Application Note (15) toward the end of this document.
1998-11-09 5/32
TOSHIBA TH58V128FT
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address /Data
( CLE)
fi-) Set-Up Time Hold Time
tDS tDH
Ilo1t08
" or "
Command Input Cycle Timing Diagram
A tCLs tCLH l
tcs tCH I
tALS tALH
tos tDH
Ilo1t08 si ie
VIH or "
1998-11-09 6/32
TOSHIBA TH58V128FT
Address Input Cycle Timing Diagram
CLE sh tCLs
tcs twc ’ twc
tWH tWH
twp tws, twr, _
m l / \ / \ /
tALS tALH
tDS _ tDH tDS tDH tos tDH
l/O1to8 A0to7 ie A9to16 A17t023 i)
" or VIL
Data Input Cycle Timing Diagram
CLE i)
Ms twc
ALE Ah
twp tum twp
tDS tDH tDS tDH tDS tDH
V01 to 8 DIN0 DIN1 DIN ** k
l V or V
** :OP=GND input: DIN 527
OP=VCC input : DlN 511
1998-11-09 7/32
TOSHIBA TH58V128FT
Serial Read Cycle Timing Diagram
|/O1~8
Status Read Cycle Timing Diagram
tCLs T
E k''1,,si) V
tWP CH tcsm
m l, / tWHC tCHZ
tWHR tOH
RE W l /
DS tDH tRHZ
- tRSTO Status
* 70H-70 in HEX data
I VIH or "
1998-11-09 8/32
TOSHIBA TH58V128FT
Read Cycle (1) Timing Diagram
CLE tCLS t(LH
tCS tCH 4%)
WE 3 l l t l ) / te t
tALS tALH tAR2
ALE l tiik
, ’ tum ERR tec
ItDS tDH tDS 2ori tREA
A9 to A17 to DOUT DOUT
A16 A23 1 N N + 1
Column address
N* th)
MT l l l
* Read Operation using 00H Command N: 0 to 255 i 7
** :OP=GND input: DOUT 527
0P=GND input: DOUT511 I " or V|L
Read Cycle (1) Timing Diagram: Interrupted by CE
CLE trLH
tcs tCH
a th Jih EI A"
l l l t t l
WE U t U te tCH2
ALS, tALH tAR2 0
ALE / 'tie- 4
tws tRR tRC
.tDS tDH tDS tDH tREA t0
A9 to A17 t DOUT Dom DOUT>
A16 A23 1 N N + 1 N + 2
Column address
R/iT l l
* Read Operation using 00H Command N: 0 to 255 '
I " or "
1998-11-09 9/32
TOSHIBA
Read Cycle (2) Timing Diagram
TH58V128FT
CLE t(LH
tCS tCH
WE l / l / l l ll tR
:ALS tALH tAR2
ALE / tiii)
, r tum ERR tec
.tDS tDH tDS tDH
=< tREA
A9 to A17 to D D
A16 A23 1 OUT DOUT OUT
Column address 256+N 256+N+1 256+N+2
N* “LB,
MT l l
* Read Operation using 01H Command N: 0 to 255 x_;
** :OP=GND input: DOUT 527
OP=Vcc input 1 DOUT 511 / I " or "
Read Cycle (3) Timing Diagram(OP=GND input)
CLE tCLH
a EI th Jih
WE l / l t t ) l tR
tALS_ tALH tAR2
ALE / 3%
tws tRR tRC
.tDS tDH tDS tDH
A9 to A17 to D D D
A16 A23) OUT OUT OUT
Column address 512+N 512+N+1 512+N+2
w “*3,
MT l /
* Read Operation using 50H Command N: 0 to 15
I " or "
1998-11-09 10/32
TOSHIBA
TH58V128FT
Sequential Read (1) Timing Diagram
CLE / N
43°; x9(00HXjir" /,,sei,,to)di,ts, M; n m [reel
Column Pagel
address aderess
Page M Page M + 1
access access
* Read Operation using 00H Command N: 0 to 255
** :OP=GND input: DOUT 527
OP=Vcc input I DOUT 511 I " or "
Sequential Read (2) Timing Diagram
I k n n "
y I? l?
R-E ..:.:':" ..:.i: _..'"
:20; MOWW saasii,toxaj,tso AIA723to
Column Page tR
address address
R/E l J
Page M
access
* Read Operation using 01H Command N: 0 to 255
** :OP=GND input: DOUT 527
OP=Vcc input : DouT 511
Page M+1
access
: " or VIL
1998-1 1-09
TOSHIBA TH58V128FT
Sequential Read (3) Timing Diagram(OP=GND input)
CLE I N
n )3 n
3,0; A WW msoxAzgo iA723to
Column Page 512 512 512
address address N N +1 N+2
R/E l 1
Page M Page M + 1
access access
* Read Operation using 50H Command N: 0 to 15
Z " or VIL
1998-11-09 12/32
TOSHIBA TH58V128FT
Auto Program Operation Timing Diagram
I/OI A0 to A9 to A17 to
to 8 A7 A1 A2
** :OP=GND input: DIN 527
OP=Vcc input: DIN 511
: " or " : If data is being output, do not allow any input.
Auto Block Erase Timing Diagram
/\f" sh/\ EE
% % JI tr"
--t/us tBERASE
ALE tvrm % Al F'"
E tos W" % I_/"
I/OI A9 to A17 to 2gggglgtgg2lielie%lgggggggt FN. Status
60H DOH 's888.' "gle%%lile%%%e%' 25;: 70H
to 8 A16 A23 " L' L' DOC.' :5; output
R/iT / f
Auto Block Erase Erase Start Status Read
Set-Up command command
command
: " or " : If data is being output, do not allow any input.
1998-11-09 13/32
TOSHIBA TH58V128FT
ID Read Operation Timing Diagram
CLE - tCLS
tCS I CHI Jcss, tcs
E I 2? l /2b-
m \ / tCR _
tALs tCH
ALH - t AR 1
- ‘x_/_\_/
RE tDS
l/OI A,.,,,-)
to 8 90H , 00 f 98H 73H
tREAID tREAID
Addres's input Make'r code Oevic'e code
I " or "
1998-11-09 14/32
TOSHIBA
TH58V128FT
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The
device pin-outs are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control the acquisition of the operation
mode command into the internal command register. The
command is latehed_into the command register from the I/O port on the
rising edge of the WE signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control the acquisition of either address
information or input data into the internal address/dg.tgL.resistor.
Address information is latched on the rising edge of WE if ALE is High.
Input data is latched if ALE is Low.
Chip Enable: CE
The device goes into a low piwer Standby mode when CE goes High
during a Read operation . The CE signal must stay Low during the Read
mode Busy state to ensure that memory gray data is correctly
transferred to the data register. quever, the CE signal is ignored when
the device is in Busy state (R/B = L) during a Progrlm or Erase
hrit1.tion, and will not go into Standby mode even if the CE input goes
Write Enable: W
The W signal is used to control the acquisition of data from the I/O
Read Enable: RE-
The RE signal coirols serial data output. Data is available tREA after
the falling edge of RE.
The internal column address counter is also incremented (Address + 1) on
this falling edge.
I/O Port: I/O 1 to 8
The I/O 1 to 8 pins are used as the port for transferring address,
command and input/output data
to or from the device.
Write Protect: WP
The WP signal is used to protect the device from accident)
programing or erasing. The internal voltage regulator is reset when WP
IS Low.This signal is usually used for protecting the data during the
power on/off sequence when input signals are invalid.
Ready/Busy: R/B
The R/B outppt signal is used to indicate the operating condition of the
device. The R/B signal is in Busy state (R/B = L) during the Program,
Erase or Read operations and will return to Ready state
(R/B = H) after completion of the operation. The output buffer for this
signal is an open drain.
o tion Pin: OP
The OP S1§nal is used to change the page size. The device is in 528
byte/page mo e when OP = GND,' and 512 byte/page mode when OP =
TH58V128FT
I/ss Cl 44 Clue
CLE l: 2 43 Cle
ALE E 3 42 DE
W I: 4 41 Cl R/E
i....y7J?....lC5 ............ 49.3.02 .....
NC I: 6 39 Cl NC
NC E 7 38 Cl NC
NC I: 8 37 Cl NC
NC I: 9 36 Cl NC
NC C10 35 Cl NC
NC I: 13 32 Cl NC
NC E 14 31 Cl NC
NC I: 15 30 Cl NC
NC I: 16 29 Cl NC
_....N.C...l.C. .17. .......... 28.3..N; .....
1/01 I: 18 27 Cl l/O8
1/02 I: 19 26 31/07
1/03 I: 20 25 Cl I/06
1/04 I: 21 24 31/05
. .... y.ss.I. 2.2. .......... ?..3..C.ly.cc.q..::
Figure l. Pinout
1998-11-09 15/32
TOSHIBA TH58V128FT
Schematic Cell Layout and Address Assignment
The Program operation is implemented in a page units while the Erase operation is carried out in
block units.
The address is read in via the I/O port over
8I/O three consecutive clock cycles, as shown in Table 1.
',,,W'''''",t A page consists of 528 bytes in which 512 bytes are for
1 main memory and 16 bytes are for redundancy or other
I - '___.____ uses.
//4:' E y 32 pages -9 1 block
" '', 1 1 Page = 528 bytes
:22: g 5 1 Block = 528 bytes x 32 pages = (16 K + 512) bytes
ll 1 1 Total Device Density = 528 bytes X 32 pages X 1024 blocks
1024blocks IL - Tl-------
Figure 2. Schematic Cell Layout
Table 1. Addressing
" 8 " 7 " 6 " 5 " 4 I/O 3 I/O 2 I/O 1
A0 to A7 : column address
First cycle A7 A6 A5 A4 A3 A2 A1 A0 A9 to A23 .' page address
A14 to A23: block address
Second cycle A16 A15 A14 A13 A12 A11 A10 A9 (A9 to A13 : NAND address in block)
Third cycle * L A23 A22 A21 A20 A19 A18 A17
*: A8 is automatically set to Low or High by a 00H command or a 01H command.
*: |/08 must be set to Low in the third cycle.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different
command operations shown 1.1L T.1l.yle _8_._ Addr..1tr... input, command input and data input/output are
controlled by the CLE, ALE, CE, WE, RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE ALE E W RE W
Command Input H L L _1_/1\_ H *
Data Input L L L U H *
Address Input L H L _1_/1\_ H *
Serial Data Output L L L H U *
During Programming (Busy) * * * * * H
During Erasing (Busy) * * * * * H
Program, Erase Inhibit * * * * * L
H: VIHI L: VILI *: " or "
1998-11-09 16/32
TOSHIBA
TH58V128FT
Table 3. Command table (HEX data)
First Cycle Second Cycle Acceptable While Busy
Serial Data Input 80 -
Read Mode (1) 00 -
Read Mode (2) 01 -
Read Mode (3) 50 -
Reset FF - C)
Auto Program 10 -
Auto Block Erase 60 D0
Status Read 70 - C)
ID Read 90 -
HEX data bit assignment
(Example)
Serial data input: 80H
r A _ r A _
|1|0|0|0|0|0|0|0|
|/08765432|/O1
Once the device has been set to Read mode by the 00H, 01H or 50H command,
additional Read commands are not needed for the following page Read operations.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE ALE CE W RE l/OI TO l/O8 POWER
Output Select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
Standby L L H H * High impedance Standby
H:V|H L:NhL *: " or "
1998-1 1-09
TOSHIBA TH58V128FT
DEVICE OPERATION
Read Mode CI)
Read mode (1) is set by issuing a 00H command to the command register. Refer to Figure 3
below for timing details and block diagram.
c-s-IgE/gl/gil
's-s.----------" A data transfer operation from the cell array to the
Start address input register starts on the rising edge of W in the third cycle
MI 527* (after the address information has been latched.) Theievice
A will be in Busy state during this transfer period. The CE
St signal must stay Low after the third address input and
Select page " Nc during Busy state.
N Cell array After the transfer period the device returns to Ready_
'Rt; Av state. Serial data can be output synchronously with the RE
clock from the start pointer designated in the address input
Figure 3. Read mode (1) operation cycle.
* When OP is Vcc Level, column address is up to 511.
Read Mode Q)
Start address input The operation of the device after input of the 01H command is
the same as that of Read mode(1). If the start pointer is to be set
256 527*
r-'1i"'zl-527/-. after column address 256, use Read mode (2).
Read mode (2) initially sets the address pointer to the second half
Seleckpage -r :,' 103” arra of the page. However, if you read past byte 527 (sequential read),
Q5 i'. Ag y then output from the next page (N + 1) starts from column address 0,
i not address 256.
Figure 4. Read mode (2)operation * When OP is at Vcc Level, column address is up to 511.
1998-11-09 18/32
TOSHIBA TH58V128FT
Read Mode 131
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in
the extra 16-byte redundancy area of the page. The start pointer is therefore assigned between bytes
512 and 527. Read mode (3) operation is invalid when OP is at Vcc Level.
CLE/_\
I/O m-- CHD-CHD- ........
A0 to A3
512 527
l 4 '" Addresses bits A0 to A3 are used to set the start pointer
g for the redundant memory cells, while A4 to A7 are ignored.
Once 50H command has been issued, the pointer moves to the
redundant cell locations and only those 16 locations can be
addressed, regardless of the A4 to A7 addresses.
A 00H command is necessary to move the pointer back to
Figure 5. Read mode(3)operation the main memory cell locations (addresses 0 to 511).
Se uential Read(1)(2)(3)
This mode allows the sequential reading of pages without additional address input.
The figure below show each operation of Sequential Read when OP is at Vcc Level.
.Jcm. "---i--------" m <--se--------" t "----v-------" t
Address input A-F Data output ‘—> Data output _-.
Busy Busy Busy
0 527 (01H) (50H) 512 527
Sequential Read (1) Sequential Read (2) Sequential Read (3)
Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above,
while Sequential Read mode (3) outputs the contents of the redundant address locations only.
When the page address reaches the next block address, read commands (OOH/ 01H/50H) and
address inputs are needed.
1998-11-09 19/32
TOSHIBA TH58V128FT
Status Read
The device automatically implements the execution and verification of the Program and Erase
operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine
the result(pass/fail) of a Program or Erase operation, and determine whether the device is in Protect
mode. The device status is output via the I/O port on the m clock after a 70H command input. The
resulting information is outlined in Table 5.
Table 5. Status output table
STATUS OUTPUT
I/OI Pass/Fail Pass : 'o' Fail : '1' . ' .
I/O2 Notused '0' wh2i't'r',aesr/sFeavi2tii',t;udotLR1,aidsyttlytfid
HO 3 Not used 'o'
I/O4 Not used 'o'
HO 5 Not used 'o'
HO 6 Not used 'o'
I/O? Ready/Busy Ready : '1' Busy : 'o'
l/O8 Write protect Protect :'0' Not Protect : '1'
An application example with multiple devices is shown in Figure 6.
CE1 c% CE3 CEN CE +1
Device Device Device Device Device
1 2 3 N N+1
E l I l I
" g 70H ' g k ( 70H ' g '
Vi''f " l Status on Istatus on
Device 1 Device N
Figure 6. Status read timing application example
SYSTEM DESIGN NOTE : If the R/B pin signals of multiple devices are common-wired as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
1998-11-09 20/32
TOSHIBA TH58V128FT
Auto Page Proggam
The device implements the Automatic Page Program operation when it receives a 10H Program
command after the address and data have been input. The sequence of command, address and
data input is shown below. (Refer to the detailed timing chart.)
80 cs--.,.,.-----'-"-?-)
Data Input Program command Status Read
command Data input command
$2155 0 to 527 when 0P=GND
0 to 511 when OP=Vcc
Data input
Program Read & Verification .
I The data is transferred (programmed) from the register to the
Selected selected page on the rising edge of W following input of the
page 10H command. After programming the programmed data is
transferred back to the register to be automatically verified by
the device. If the program does not succeed, the above
Program/Verify operation is repeated by the device until success is
achieved or until the maximum loop number set in the device is
Figure 7. Auto Page Program operation reached.
I MT automatically returns to Ready after completion.
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of ITrTif after the Erase Start command DOH
which follows the Erase Set-Up command 60H. This two-cycle process for Erase operations acts as an
extra layer of protection from accidental erasure of data due to external noise. The device
automatically executes the Erase and Verify operations.
CEN Ciiit 1'0C/tiyr''a-ss
60 D0 70
l Fail
Block address . Erase Start Status Read
input: 2cycles command command
R/B l Busy /
1998-11-09 21/32
TOSHIBA TH58V128FT
The Reset mode stops all operations. For example, in the case of a Program or Erase
operation the regulated voltage is discharged to 0 volts and the device will go into Wait state.
The address and data registers are set as follows after a Reset:
. Address Register : A11 '0'
. Data Register : All '1'
. Operation Mode : Wait State
The response after an FFH Reset command is input during the various operations are as follows:
co When a Reset (FFH) command is input during programming
(80} tlo', 'FF', foo',
Nu''.',,-' V'-'.--'" \J
. Register set
Internal Vpp -l"rrsssci)'i, Fi'
tRST (max IOM;) I
© When a Reset (FFH) command is input during erasing
g ' 1'Cii.''.) CiD-
ue.?.,,.) Ct . 00
Internal Erase _l-tri."sss-s-., . Register set .
voltage 3 :"-t:
_ EA tRST (max 500ps) Lg
R/B I i" s)
3 When a reset(FFH) command is input during a Read operation
m—\ El
iM-F.'
tRST (max 6/15)
(5) When a Status Read command (70H) is input after a Reset
l FF , CiiD---,
l l/O status : Pass/ Fail -> Pass
: Ready/ Busy -9 Ready
However, the following operation is prohibited. If the following operation is executed, set up
for address and data register can not be guaranteed. (the Register may not be reset correctly)
C . CEN- I/O status : Ready/Busy -9 Busy
(B) When two or more Reset command are input in succession
(1) (2) (3)
, 10 k ' FF E , FF k FF
'sd2.9 VL'.." K:
MT I I
The second CD command is invalid, but the third CD command is valid.
1998-11-09 22/32
TOSHIBA
TH58V128FT
ID Read
The TH58V128 contains ID codes which identify the device type and the manufacturer. The ID
codes can be read out using the following timing conditions:
CLE l (
tREAID
90H 00 98H
ID Read command Address Maker code
Device code
For the specification of the access times tREAID, tce and tAR1 refer to the AC Characteristics.
Table 6. Code table
I/O 8 l/O 7 " 6 HO 5 IIO 4 1/0 3 " 2 " 1 HEX DATA
Maker code 1 0 0 1 1 0 0 98H
Device code 0 1 1 1 0 0 1 73H
1998-11-09 23/32
TOSHIBA TH58V128FT
APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands
The operation commands are listed in Table 3. Data input as a command other than the
specified commands in Table 3 is prohibited. Stored data may be corrupted if an unspecified
command is entered during the command cycle.
(2) Restriction of command while Busy state
During Busy state, do not input any command except 70H and FFH.
(3) Pointer control for 00H, 01H, 50H
The device has three read modes which set the destination of the pointer. Table 7 shows the
destination of the pointer, and figure 14 shows the block diagram of their operations.
0 255 256 511 512 527
READ MODE COMMAND POINTER III ..................... (Lu ........................ lll ..... l
(1) 00H 0 to 255 3 I /
(2) 01H 256 to 511 'l/
(3) 50H 512 to 527 00H "
01H -F Pointer control
50H -F
Table 7. Pointer Destination
Figure 8. Pointer control
The pointer is set to region A by the 00H command, to region B by the 01H command,
and to region C by the 50H command.
(Example)
The 00H command needs to be input to set the pointer back to region 'A' when the pointer
points to region C.
00H , 50H _
Add Start point Add Start point Add Start point
A area A area C area
50H , 00H k
"s--------------" s-----------"::".''
Add Start point Add Start point Add Start point
C area C area A area
's---------------" u-v---"
Add Start point Add Start point
B area A area
For programming into region C only, set the start point to region C with the 50H command.
, 80H k l _
50H 'cr-c"----'--------"::-'.'-'"----,,.--------"
Add DIN . . .
l Programming into region C only
Start point
C area
ram? fob
01H c-u"-----"---------'-''''"---.----------"
Add DIN . . .
Programming Into region B and C
Start point
B area
1998-11-09 24/32
TOSHIBA TH58V128FT
(4) Acceptable commands after Serial Input command 80H
Once the Serial Input command (80H) has been input, do not input any command other than the
Program Execution command 10H or the reset command FFH.
CiiD \Ff/
m -1uiCluit .
"---v-----"
Address input
R/E \—/
If a command other than 10H or FFH is input, the program operation is not performed.
80 , XX . , 10 ' . .
_ 1 In case of this operation, the FFH command
Other command Programming will not be executed. is needed.
than 10H or FFH
(5) Status Read during the Read operation
u-tci-ii?-......
Command CD
E_\ Cl
m Ll \Al l I l I i'
m l i." Ii
RE address N Status'Read \_L ' . L/NI.-
. -_-I
command input
Status Read Status output
The device status can be read out by inputting the Status Read command(70H).
Once the device has been set to the Status Read mode by the 70H command , the device will not return
to Read mode.
Therefore, a Status Read during the Read mode is prohibited.
However, if the Read command (00H) is input during [A], the Status Read mode will be terminated,
and the device will return to the Read mode. Then, data output will start from address N without
address input.
(6) Auto programming failure
/-\ Fail fc,",',"'"', f",7,'.>s
80 IO 70 " 80 10
CiiDs, s-NCL'..,, _d2,'..Mss,- ss..ldl.1.,M
Address Data Address Data
M input N input
When the programming result for page address M is Fail, try to program the page
to address N in another block. Because the previous input data is lost, the same
sequence of 80H command, address and data input is necessary.
Figure 9.
1998-11-09 25/32
TOSHIBA TH58V128FT
(7) MT .' termination for the Ready/ Busy pin (R/tT)
A pull-up resistor needs to be used for termination because the MT buffer consists of an open
drain circuit.
v Vcc R . i' .' : i'
Device R/IT i.' i . Busy y, . Q i.'.
CL : i Hi :
" l . t,
Vcc= 3.3 V
vy I.5ys Ta=25°C 15ns
t CL = 100 pF
t, 1.0 td; 10 ns
0.5 s Sns
This data may vary by device. 'u :
We recommend that you use this data as a I i I I
reference when selecting a resistor value. 0 1kt2 2kt2 3kt2 4kn
(8) Status after Power On
The following sequence is necessary because same input signals may not be stable at power on.
Power on -CD-
(9) Power On/ Off Sequence:
The W signal is useful for protecting against data corruption at power on/ off. The following
timing sequence is necessary :
3.0V, :
2.8V i s tt
VIH ':.'
- VIL 5 i..' VIL
WP - : Operation c.'
Figure 10. Power On/Off Sequence
1998-11-09 26/32
TOSHIBA TH58V128FT
(10) Note regarding BTP- Signal
The Erase and Program operations are compulsively reset when Ttfri goes Low. The Operations
are enable and disable as follows :
Enable Proggamming
m —.‘_I—I_I—
ip"''7,7,'h f-cs
DIN I i‘ 80 ' , 10 '
R/E A w' I
100ns min
Disable Progamming
DIN y _ ' _
l i' 80 , , 10 ,
W I l,
R/é l l,
100ns min
Enable Erasing
'/'C'CC'N wt'.'',".?,"'',
DIN I i‘ 60 , , D0 ,
R/E A w', I
100ns min
Disable Erasing
m —.‘_I—I_J—
DIN ',
I 'f 60 l ( D0 )
R/E A w'
100ns min
1998-11-09 27/32
TOSHIBA TH58V128FT
(11) When four address cycles are input
Although the device may acquire the fourth address, it is ignored inside the chip.
Read operation
"o-CD-t H H Ai:-
00H, 01H or 50H Address input ignored
R/iT \
Internal read operation starts when TiTtf goes High in the third cycle.
Program ogeration
ALE / \
I/o-er-ily-ty-tHy-ty-tHy-ty--
'r,cc:sc',c''!"-oaccccr'-'"-"
Address input Data Input
ignored
1998-11-09 28/32
TOSHIBA TH58V128FT
(12) Divided program in the same page (Partial page program)
The device allows a page to be divided into 10 segments (maximum) with each page segment
programmed individually as follows:
The first programming
Column A Column B
Page N Data Pattern1
The second programming
Page N Data Pattern2
The third programming
Page N ~ Data Pattern3
Result
Column A Column B ColumnC ColumnD ColumnE ColumnF
Page N Data Pattern1 Data Pattern 2 Data Pattern 3
Figure 11.
Note: The input data for unprogrammed or previously programmed page segments must be '1'.
(Le. Mask all page bytes outside the segment to be programmed with 'I' data.)
(13) Note regarding the TtTil" Signal
The internal column address counter is incremented synchronously with the 1Thf clock in the read
mode. Therefore, once the device has been set to read mode by aOOH, 01H or 50H command, the
internal column address counter is incremented by the E clock independently of (before or after) the
address input. Assuming that the W clocks are inputted before address input and the pointer
reaches the last column address, internal read operation (array-' register) will occur and the device
will be in Busy state.
Address input
00H/01H
Therefore, ITE clocks must occur after the address input.
1998-11-09 29/32
TOSHIBA TH58V128FT
(14) Invalid block (bad block)
The device contains unusable blocks. Therefore, the following issues must be recognized:
Check if the device has any bad blocks after device installation into
the system. Do not try to access bad blocks. A bad block does not
_ Bad Block affect the performance of good blocks because it is isolated from the bit
line by the select gate.
The number of valid blocks is as follows:
Table 8.
_ Bad Block MIN TYP MAX UNIT
Valid (Good) Block Number 1004 1016 1024 Block
Figure. 12
Figure 14 shows the bad block test flow.
(15) Failure Phenomena for Program and Erase Operations.
The device may fail during program or erase operation.
The following possible failure modes should be considered when implementing a highly reliable
system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase -9 Block Replacement
Page Program Failure Status Read after Prog. - Block Replacement
Single Bit* Program Failure (1) Block Verify after Prog. -> Retry
'I'-y'0' (2) ECC
* : (1) or (2)
0 ECC : Error Correcting code _ Hamming Code etc.
Example .' 1 bit correction & 2bit detection.
0 Block Replacement
Program
error occurs
When an error happens in Block A, try to
Buffer
reprogram the data into another (Block B) by
memory 1
Block A
loading from an external buffer. Then, prevent
further system accesses to Block A ( by creating
a bad block table or by using an another
Block B appropriate scheme).
Figure. 13
When an error occurs for an erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using other appropriate scheme).
1998-11-09 30/32
TOSHIBA TH58V128FT
BAD BLOCK TEST FLOW
C : Checker board pattern
E : Invert checker board pattern
Blank check : 1 Block read (FFH)
Test Start
Block No = 1
Block No = 1
32Page" Fail
C - Patt Proc
Read(00H) Fail
Block Fail No
Erase Bad
Pass Block B No. = 1024
2 Pail - Fail
/C - Patt Prog Yes
Read(00H) Fail
Block Fail
BNo.--BNo.+1l-
B No. = 1024
Test End
Figure 14.
1998-11-09 31/32
TOSHIBA TH58V128FT
PACKAGE DIMENSIONS
TSOPII44.40-P-400-0.80J
UNITS: mm
44 35 32 23
flf)flf)flfHHHHl HHHUHHHHUH -
jtstststn)iiLttpp 1tlrl1rll1vl"ll2-- E)
a ioarvp -.,i-ii8-j i-10 0.31:0.06m
18.8MAX _ x 'ii')
13.4201 3% 'ic'ii:-i,,:,,zzfz,,)
0.1 9610.1
0.1i0.05
0.8+0.2
1998-11-09 32/32

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