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TFP501PZPTIN/a10841avaiPanelBus <TM> HDCP Digital Receiver
TFP501PZPTEXASN/a89avaiPanelBus <TM> HDCP Digital Receiver


TFP501PZP ,PanelBus <TM> HDCP Digital ReceiverBLOCK DIAGRAM3.3 V 3.3 V1.8 VRegulatorInternal 50 ΩTerminationRED[7:0] RED[7:0]QE[23:0]Channel 2CH2 ..
TFP501PZP ,PanelBus <TM> HDCP Digital ReceiverFEATURES DESCRIPTIONThe TFP501 is a Texas Instruments PanelBus flat2• Supports Pixel Rates Up to 16 ..
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TFP501PZP
PanelBus <TM> HDCP Digital Receiver
TFP501
www.ti.com
SLDS127C –JULY 2001–REVISED JULY 2011
PanelBus
HDCP Digital Receiver
Checkfor Samples: TFP501
1FEATURES DESCRIPTION

The TFP501isa Texas Instruments PanelBus flat Supports Pixel Rates Upto 165 MHz (including panel display product, partofa comprehensive family1080p and WUXGAat 60Hz) of end-to-end DVI 1.0-compliant solutions. Targeted• Digital Visual Interface (DVI) and primarily at desktop LCD monitors, DLP and LCDHigh-Bandwidth Digital Content Proataection projectors, and digital TVs, the TFP501 finds(HDCP) Specification Compliant(1)
applicationsin any design requiring high-speed digital• Encrypted External HDCP Device Key Storage interface with the additional benefitof an extremelyfor Exceptional Security and Easeof robust and innovative encryption scheme for digitalImplementation content protection.• True-Color, 24 Bits/Pixel, 48-bit Dual Pixel The TFP501 supports display resolutionsupto 1080pOutput Mode, 16.7M Colorsat1or2 Pixels Per and WUXGAin 24-bit true color pixel format. TheClock TFP501 offers design flexibilityto drive oneor two• Laser Trimmed (50-Ω) Input Stage for Optimum pixels per clock, supports TFTor DSTN panels, andFixed Impedance Matching provides an option for time staggered pixel outputs• Skew Tolerant upto One Pixel Clock Cycle for reduced ground-bounce.(High Clock and Data Jitter Tolerance) PowerPAD advanced packaging technology resultsin• 4x Over-Sampling for Reduced Bit-Error Rates best-of-class power dissipation, footprint, andand Better Performance Over Longer Cables ultra-low ground inductance.• Reduced Power Consumption From 1.8-V Core
The TFP501 combines PanelBus circuit innovationOperation With 3.3-V I/O's and Supplies(2)
and unique implementation for HDCP key protection• Reduced Ground-Bounce Using Time with TI's advanced 0.18 µm EPIC-5 CMOS processStaggered Pixel Outputs technologyto achievea completely secure, reliable,• Lowest Noise and Best Power Dissipation low-powered, low noise, high-speed digital interfaceUsingTI 100-pin TQFP PowerPAD ™Packaging solution.• Advanced Technology Using TI's 0.18-mm
EPIC-5™ CMOS Process
Supports Hot Plug Detection
(1) The digital visual interface (DVI) specificationisan industry
standard developedbythe digital display working group
(DDWG)for high-speed digital connectionto digital displays.
The high-bandwidth digital content protection system (HDCP) protecting DVI outputs from being Corporation andis LLC. The TFP501 HDCP Rev.1.03.3
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