TDA9206 Fast Delivery |IC PHOENIX CO.,LIMITED

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TDA9206
I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
TDA92062C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
September 1996
DIP24
(Plastic Package)
ORDER CODE: TDA9206
.130MHz TYPICAL BANDWIDTH AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD.2.8ns TYPICAL RISE/FALL TIME AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD.POWERFULL OUTPUTDRIVE CAPABILITY.BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH AREI2C BUS CONTROLLED.INTERNAL BACK-PORCH CLAMPING
PULSE GENERATOR.OSD WHITE BALANCE TRACKING.INTERNAL OSD SWITCHES.BLANKING AND FAST-BLANKING INPUTS.VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB) .SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
DESCRIPTION
The TDA9206isa digitaly controlled wideband
video preamplifier intendedfor usein high resolu-
tion color monitor.All controls and adjustments are
digitaly performed thankstoI2C serial bus. Con-
trast, brightness and DC output levelof RGB sig-
nals are commonto the3 channels and drive
adjustmentis separatefor each channel.ThreeI2C
gain controlled OSD inputs canbe switched with
RGB signalsusing fast blanking command. Clamp-
ingof RGBsignalsis performed thankstoa flexible
integrated system. The white balance adjustment effectiveon brightness, video and OSD signals.
The TDA9206worksfor application usingACor DC
coupled CRT driver.
Becauseof its features and dueto component
savingthe TDA9206leadsto avery performantand
cost effective application.
HSYNC
PVCC1
OUT1
PGND1
PVCC2
OUT2
PGND2
PVCC3
OUT3
PGND3
BLK
FBLK
IN1
OSD1
AVDD
IN2
OSD2
AGND
IN3
OSD3
LVDD
LGND
SDA
SCL
9206-01.EPS
PIN CONNECTIONS
1/12
Name Pin Type Function
IN1 1 I 1st Channel Main Picture Input
OSD1 2 I 1st Channel OSD Input
AVDD 3 I 12V Analog VDD
IN2 4 I 2nd Channel Main Picture Input
OSD2 5 I 2nd Channel OSD Input
AGND 6 I/O Analog Ground
IN3 7 I 3rd Channel Main Picture Input
OSD3 8 I 3rd Channel OSD Input
LVDD 9 I 12V Logic VDD
LGND 10 I/O Logic Ground
SDA 11 I/O Serial Data Line
SCL 12 I Serial Clock Line
Name Pin Type Function
FBLK 13 I Fast Blanking Input
BLK 14 I Blanking Input
PGND3 15 I/O 3rd Channel Power Ground
OUT3 16 O 3rd Channel Output
PVCC3 17 I 3rd Channel Power VCC
PGND2 18 I/O 2nd Channel Power Ground
OUT2 19 O 2nd Channel Output
PVCC2 20 I 2nd Channel Power VCC
PGND1 21 I/O 1st Channel Power Ground
OUT1 22 O 1st Channel Output
PVCC1 23 I 1st Channel Power VCC
HSYNC 24 I Horizontal Synch Input
9206-01.TBL
PIN DESCRIPTION 1214
CLAMP
VREF
AVDD
IN1
AGND
IN2
BRIGHTNESS
IN3
OUTPUT
STAGE
DRIVEbits
BPCP
PVCC1FBLKBLK
OUT1
PGND1
PVCC2
OUT2
PGND2
OUT3
PGND3
PVCC3LVDD
LGND
I2C
BUS
DECODER
D/A
LATCHESBPCP
SCLSDAHSYNC
OSD
OSD1 OSD2 OSD3
GREEN CHANNEL
BLUE CHANNEL
I2C
VREF
OUTPUT LEVEL
ADJUST
TDA9206
CONTRAST
CONT
9206-02.EPS
BLOCK DIAGRAM
TDA9206
2/12
BLK
HSYNC
BPCP
Internal pulse widthis controlledbyI2C
9206-04.EPS
Figure1
HSYNC
BPCP
Internalpulsewidthis controlledbyI2C
9206-05.EPS
Figure2
FUNCTIONAL DESCRIPTION
Input Stage
TheR,G andB signals mustbe fedto the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude 1V.
The input stage includesa clamping function. This
clampis using the input serialcapacitoras ”mem-
ory capacitor” andis gatedbyan internally gener-
ated ”Back-Porch-Clamping-Pulse (BPCP)”.
The synchronizationedgeof the BPCPis selected
accordingbit0of register R8.
When B0R8is setto1, the BPCPis synchronized the leading edgeof the blanking pulse BLK
inputson Pin14 (see Figure1).
When B0R8is clearto0, theBPCPis synchronized thesecondedgeof the horizontalpulse HSYNC
inputson Pin 24. An automatic function allowsto
use positiveor negative horizontal pulseon Pin24
(see Figure2). both case BPCP widthis adjustablebyI2C, B1
and B2of register R8 (see R8 Table P8).
Contrast Adjustment(8 bits)
The contrast adjustmentis made by controlling
simultaneously the gainof three internal variable
gain amplifiers through theI2C bus interface.
The contrast adjustment allowsto covera typical
rangeof 48dB.
Brightness Adjustment(8 bits) for the contrast adjustment, the brightnessis
controlledbyI2C.
The brightness function consiststo add the same offsetto the threeR,G,B signals after contrast
amplification.
This DC-Offsetis present only outsidethe blanking
pulse (see Figure 3).
The DC output level during the blanking pulse,is
forcedto ”INFRA-BLACK” level (VDC).
Drive Adjustment(3x8 bits) orderto adjust the white balance, the TDA9206
offersthe possibilityto adjust separately theoverall
gainof each complete video channel.
The gainof each channelis controlledbyI2C (8bits
each).
The very large drive adjustment range(48dB) allows
different standardor custom color temperature. can alsobe usedto adjust the output voltagesat
the optimum amplitudeto drive the C.R.T drivers,
keepingthe wholecontrast controlfor end-useronly.
The drive adjustmentis located after the CON-
TRAST, BRIGHTNESS and OSD switch blocks,so
that the white balance will remains correct when
BRTis adjusted, and will alsobe correcton OSD
portionof the signal.
OSD Inputs
The TDA9206 includesall the circuitry necessary mix OSD signalsinto the RGB main-picture. Four
pins are dedicatedto this functionas follow.
Three TTL RGB On Screen Display inputs
(Pin2,5 and8). These three inputs areconnected the three outputsof the corresponding ON-
SCREEN-DISPLAY processor (ex: STV942x).
One Fast Blanking Input (FBLK, Pin 13) whichis
also connectedto the FBLK outputof the same
ON-SCREEN-DISPLAY processor.
Whena high levelis presenton FBLK, theIC will
actsas follow: The three main picture RGB input signals are
internally switchedto the internal input clamp
reference voltage. The three output signals are setto voltages
correspondingto the state(0or1)on the three
OSD inputs(see Figure3).
Example: FBLK=1 and OSD1, OSD2, OSD3)=1,0,1
respectively.
Then OUT1, OUT2, OUT3 will be equalto VOSD,
VBRT,VOSD,
where: VBRT =VBLACK +BRT
VOSD =VBRT+ OSD
BRTis the brightnessDC levelI2C adjustable.
OSDis the On-Screen Display signal valueI2C
adjustable from 0Vto 4.68VPPby stepof 0.312V.
Semi-transparent functionis controlled thanksto
Bit6of R8 register (seeT able1).
When semi-transparent modeis activated, video
signalis dividedby2 (CONT).
TDA9206
3/12
FUNCTIONAL DESCRIPTION (continued)
Table1
FBLK OSD1 OSD2 OSD3 B6R8 Output
Signal (OUTn) x x x 0 Video x x x 0 OSD(1) x x x 1 Video
10x x 1 OSD x 1 x 1 OSD x x 0 1 OSD 1 0 1 1 Semi-trans-
parent(2)
Notes:1. AllOSD colorsare displayed. One OSD coloris displayedas semi-transparent video
without effecton brightnessandDC level adjustment.
Output Stage
The threeoutput stages incorporatethreefunctions
which are: The blanking stage: When high levelis applied the BLK input (Pin 14), the three outputs are
switchedtoa voltage whichis 400mV lower than
the BLACK level. The black levelis the output
voltage with minimum brightness when input
signal video amplitudeis equalto ”0”. The output stage itself:Itisa large bandwidth
output amplifier which allowto deliverupto 5VPP the three outputs(for 0.7V video signalon the
inputs). The typical bandwidthis 100MHzat -3dB
measured with 4VPP output signalon 12pF load. The output CLAMP: TheIC also incorporates
three internal output clamp (sample and hold
system) which allowto DC shift the three output
signals. The DC output voltageis adjustable
throughI2C with4 bits. Practicaly, the DC output
level allowto adjust the BLK level
(VDC= 400mV under VBLACK) from 0.9Vto 2.9V
with12x 165mV.
The overall waveforms of the output signal ac-
cordingto the different adjustment are shownin
Figures3 and4.
Serial Interface
The 2-wires serial interfaceisanI2C interface.
The slave addressof the TDA9206is DC(in hexa-
decimal). A5 A4 A3 A2 A1 A0 W
110 111 00
Data Transfer
The host MCU can write data into the TDA9206
registers. Read modeis not available. write data into the TDA9206, aftera start, the
MCU must send (see Figure5): TheI2C address slave byte witha low levelfor the
R/W bit. The byteof the internal register address where
the MCU wantsto write data(s). The data.
All bytes are sent MSBbit first and the write data
transteris closedbya stop.
HSYNC
VCONT(4)
BPCP
BLK
VideoIN
FBLK
OSDIN
VOSD(5)
VBRT(3)
VBLACK(2)
VDC(1)
CONTOSD
BRT
0.4V fixed
VOUT1,VOUT2,VOUT3
Notes:1. VDC= 0.5to2.5V VBLACK=VDC+ 0.4V VBRT=VBLACK+BRT (with BRT=0to 2.5V) VCONT =VBRT +CONTwith CONT=kx VideoIN (CONT=5VPP max.forVIN =0.7VPP) VOSD =VBRT+ OSDwith OSD=k1x OSDIN(OSD max. =5VPP, OSDmin.= 312mVPP)
9206-06.EPS
Figure3: Waveforms VOUT, BRT, CONT, OSD
TDA9206
4/12
HSYNC
VCONT
BPCP
BLK
VideoIN
FBLK
OSDIN
VOSD
VBRT
VBLACKDC OUT1,V OUT2,VOUT3
Note:1. Drive adjustment modifiesthe following voltages: VCONT,VBRTand VOSD.
Drive adjustmentdonot modifythe following voltages:VDCand VBLACK.
Two examples drive adjustment(1)
9206-07.EPS
Figure4: Waveforms (DRIVE adjustment)
SCL A7 A6A5 A4 A3 A2A1 A0SDA
RegisterAddress ACKACKI2C SlaveAddressStart D6 D5D4 D3 D2D1 D0
DataByte ACK Stop
9206-08.EPS
Figure5:I2C Write Operation
FUNCTIONAL DESCRIPTION (continued)
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit
Signal Bandwidth (2VPP/12pF load) 130 MHz
Rise and Fall Time (2VPP/12pF load) 2.8 ns
Drive Adjustment Rangeonthe3 Channels separately 48 dB
Maximum Output Voltage (VIN=0.7 VPP)5 V
Output Voltage Range (AC+ DC) 8 V
9206-02.TBL
TDA9206
5/12
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit Supply Voltage (Pins3-9-17-20-23) 14 V
VIN1
VIN2
Voltageat any Input Pins (except SDA& SCL)
Voltageat any Input Pins (on SDA& SCL)
GND< VIN1 GND< VIN2< 5.5
VESD ESD Susceptability (Human body model; 100pF Discharge through 1.5kΩ)2 kV
Tstg Storage Temperature -40,+ 150 °C Junction Temperature 150 °C
Toper Operating Temperature 0,+70 °C
9206-03.TBL
THERMAL DATA
Symbol Parameter Value Unit
Rth(j-a) Junction-ambient Thermal Resistance 62 o C/W
9206-04.TBL ELECTRICAL CHARACTERISTICS (Tamb =25oC, VCC= 12V, unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit Supply Voltage Pins 3-9-17-20-23 11.4 12 12.6 V Supply Current (AllVS Pin current) RL =1kΩ 90 mA Video Input Voltage Amplitude Pins 1-4-7 0.7 1 VPP Typical Output Voltage Range Pins 16-19-22 0.5 - 8 V
VIL OSD Low Level Inputs OSD, FBLK, BLK, HSYNC Pins2,5,8, 13,14,24 0.8 V
VIHOSD High Level Inputs OSD, FBLK, BLK, HSYNC Pins2,5,8, 13,14,24 2.4 V
9206-05.TBL ELECTRICAL CHARACTERISTICS
(Tamb =25oC, VCC= 12V,CL= 12pF,RL =1kΩ , unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit Maximum Gain (20logx VOUTAC/VINAC) Contrast& Driveat maximum 18 dB
CAR Contrast Attenuation Range VIN= 0.7V, BRT, Drive= POR 48 dB
DAR Drive Attenuation Range VIN= 0.7V, Contrast, Drive= POR 48 dB Gain Match VOUT= 2.5VPP,VIN= 0.7VPP
Contrast= Drive= Maxix 0.7 (POR) 0.1 dB
Bandwidth LargeSignal
Bandwidth Small Signal -3dB,VIN= 0.7VPP
VOUT =4VPP,
Contrast= Drive= Maxix 0.87
VOUT =2VPP,
Contrast= Drive= Maxix 0.62
MHz
MHz
DIS Video Output Distorsion (see Note) f= 1MHz, VOUT =1VPP,VIN =1VPP 0.3 %
tR,tF Video Output Rise and Fall Time
(see Note)
VIN= 0.7VPP,
VOUT =4VPP
Contrast= Drive= Maxix 0.87
VOUT =2VPP
Contrast= Drive= Maxix 0.62
4.5 ns
BRT Brightness Maximum DC Level
Brightness Minimum DC Level
BRTM Brightness Matching BRT= 50%, Drive= POR ±20 mV
Note: POR= Power-on Reset Value
9206-06.TBL
TDA9206
6/12

Partno	Mfg	Dc	Qty	Available	Descript
TDA9206	ST	N/a	488	avai	I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER