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TDA8024ATNXPN/a443avaiStandard smart card interface
TDA8024TPHN/a97avaiStandard smart card interface
TDA8024TTNXPN/a148avaiStandard smart card interface


TDA8024AT ,Standard smart card interfaceGENERAL DESCRIPTION13 APPLICATION INFORMATION4 ORDERING INFORMATION14 PACKAGE OUTLINES5 QUICK REFER ..
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TDA8024AT-TDA8024T-TDA8024TT
Standard smart card interface

Philips Semiconductors Product specification
IC card interface TDA8024
CONTENTS
FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
8.1 Power supply
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ
(or with TDA8024AT)
8.2.2 With an external divider on pin PORADJ (not
for the TDA8024AT)
8.2.3 Application examples
8.3 Clock circuitry
8.4 I/O transceivers
8.5 Inactive mode
8.6 Activation sequence
8.7 Active mode
8.8 Deactivation sequence
8.9 VCC generator
8.10 Fault detection LIMITING VALUES HANDLING THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING
15.1 Introduction to soldering surface mount
packages
15.2 Reflow soldering
15.3 Wave soldering
15.4 Manual soldering
15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
Philips Semiconductors Product specification
IC card interface TDA8024 FEATURESIC card interface3or5 V supply for the IC (VDD and GND) Three specifically protected half-duplex bidirectional
buffered I/O lines to card contacts C4, C7 and C8 DC/DC converter for VCC generation separately
powered from a 5V± 20% supply (VDDP and PGND) 3or5V± 5% regulated card supply voltage (VCC) with
appropriate decoupling has the following capabilities:
–ICC<80 mA at VDDP=4to 6.5V Handles current spikes of 40 nAs up to 20 MHz Controls rise and fall times Filtered overload detection at approximately 120 mA Thermal and short-circuit protectiononall card contacts Automatic activation and deactivation sequences;
initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating, VDD or VDDP
drop-out Enhanced ESD protection on card side (>6 kV) 26 MHz integrated crystal oscillator Clock generation for cards up to 20 MHz (divided by2,4or 8 through CLKDIV1 and CLKDIV2 signals)
with synchronous frequency changes Non-inverted control of RST via pin RSTIN ISO 7816, GSM11.11 and EMV (payment systems)
compatibility Supply supervisorfor spike-killing during power-on and
power-off and Power-on reset (threshold fixed internally
or externally by a resistor bridge); not for TDA8024AT Built-in debounce on card presence contacts One multiplexed status signal OFF. APPLICATIONSIC card readers for banking Electronic payment Identification Pay TV. GENERAL DESCRIPTION
The TDA8024 is a complete and cost-efficient analog
interfacefor asynchronous3or5V smart cards.It canbe
placed between the card and the microcontroller to
perform all supply, protection and control functions. Very
few external components are required. TheTDA8024ATis
a direct replacement for the TDA8004AT.
More information canbe obtained from the Philips Internet
site ( ) and from
“Application note AN10141”. ORDERING INFORMATION
Philips Semiconductors Product specification
IC card interface TDA8024 QUICK REFERENCE DATA
Philips Semiconductors Product specification
IC card interface TDA8024 BLOCK DIAGRAM
Philips Semiconductors Product specification
IC card interface TDA8024 PINNING
Note
The noise margin on VCC will be higher with the 220 nF capacitor.
Philips Semiconductors Product specification
IC card interface TDA8024
Philips Semiconductors Product specification
IC card interface TDA8024 FUNCTIONAL DESCRIPTION
Throughout this documentitis assumed that the readeris
familiar with ISO7816 terminology.
8.1 Power supply

The supply pins for the IC are VDD and GND. VDD should
be in the range of 2.7to 6.5 V. All signals interfacing with
the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader
contacts remain inactive during power-on or power-off.
The internal circuits are maintainedin the reset state until
VDD reaches Vth2 +Vhys2 and for the duration of the
internal Power-on reset pulse, tW (see Fig.5). When VDD
falls below Vth2,an automatic deactivationof the contacts
is performed.
A DC/DC converter is incorporated to generate theor3V card supply voltage (VCC). The DC/DC converter
shouldbe supplied separatelyby VDDP and PGND. Dueto
the possibility of large transient currents, the two 100nF
capacitors of the DC/DC converter should be located as
near as possible to the IC and have an ESR less than
100 mΩ.
The DC/DC converter functions as a voltage doubler or a
voltage follower accordingto the respective valuesof VCC
and VDDP (both have thresholds with a hysteresis of
100 mV).
The DC/DC converter function changes as follows: VCC=5 V and VDDP> 5.8 V; voltage follower VCC=5 V and VDDP< 5.7 V; voltage doubler VCC=3 V and VDDP> 4.1 V; voltage follower VCC=3 V and VDDP< 4.0 V; voltage doubler.
Supply voltages VDD and VDDP maybe appliedto theICin
any sequence.
After powering the device, OFF remains LOW until
CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the
falling threshold voltage.
8.2 Voltage supervisor

8.2.1 WITHOUT EXTERNAL DIVIDERON PIN PORADJ
(OR WITH TDA8024AT)
The voltage supervisor surveys the VDD supply.A defined
reset pulseof approximately8 ms (tW)is used internallyto
keep the IC inactive during power-on or power-off of the
VDD supply (see Fig.5).
As long as VDD is less than Vth2 +Vhys2, the IC remains
inactive whatever the levels on the command lines. This
state also lastsfor the durationoftW after VDD has reached
a level higher than Vth2 +Vhys2.
When VDD falls below Vth2,a deactivation sequenceof the
contacts is performed.
Philips Semiconductors Product specification
IC card interface TDA8024
8.2.2 WITHAN EXTERNAL DIVIDERON PIN PORADJ (NOT
FOR THE TDA8024AT)an external resistor bridgeis connectedto pin PORADJ
(R1 and R2 in Fig.1), then the following occurs: The internal threshold voltage Vth2 is overridden by the
external voltage and by the hysteresis, therefore:
where Vbridge= 1.25V typ. and Vhys(ext)=60 mV typ. The reset pulse width tW is doubled to approximately ms.
Input PORADJis biased internally with apull-down current
source of 4 μA which is removed when the voltage on
pin PORADJ exceeds 1 V. This ensures that after
detectionof the external bridgeby theIC during power-on,
the input current on pin PORADJ does not cause
inaccuracy of the bridge voltage.
The minimum threshold voltage shouldbe higher than2V.
The maximum threshold voltage may be up to VDD.
8.2.3 APPLICATION EXAMPLES
The voltage supervisoris usedas Power-on reset andas
supply dropout detection during a card session.
Supply dropout detection is to ensure that a proper
deactivation sequenceis followed before the voltageis too
low.
For the internal voltage supervisorto function, the system
microcontroller should operate downto 2.35Vto ensurea
proper deactivation sequence. If this is not possible,
external resistor values can be chosen to overcome the
problem.
8.2.3.1 Microcontroller requiring a 3.3V ±20% supply
For a microcontroller supplied by 3.3 V with a ±5%
regulator and with resistors R1, R2 having a ±1%
tolerance, the minimum supply voltage is 3.135V.
VPORADJ =k× VDD, where with S1 andS2
the actual values of nominal resistors R1 and R2.
This can be shown as
0.99×R1< S1< 1.01× R1 and
0.99×R2< S2< 1.01× R2
Transposed, this becomes
If V1= Vth(ext)(rise)(max) and V2= Vth(ext)(fall)(min)
activation will always be possible if VPORADJ >V1
and deactivation will always be done for VPORADJ< V2.
Activation is always possible for
and deactivation is always possible for .
That is V1= 1.31 V and V2= 1.19V
and
Suppose R1+ R2= 100 kΩ, then 42.3 kΩ and R1= 57.7 kΩ.
Deactivation will be effective at×(1+ 1.02× 1.365)= 2.847 V in any case. the microcontroller continuesto function downto 2.80V,
the slew rateon VDD shouldbe less than2 V/msto ensure
that clock CLK is correctly delivered to the card until
timet12 (see Fig.9).
8.2.3.2 Microcontroller requiring a 3.3V ±10% supply
For a microcontroller supplied by a 3.3 V with a ±1%
regulator and with resistors R1, R2 having a ±0.1%
tolerance, the minimum supply voltage is 3.267V.
The same calculations as in Section 8.2.3.1 conclude:
Therefore = 40.14 kΩ and R1= 59.86 kΩ.
Deactivation will be effective at×(1+ 1.002× 1.491)= 2.967 V in any case. the microcontroller continuesto function downto 2.97V,
the slew rate on VDD should be less than 0.20 V/ms to
ensure that clock CLK is correctly delivered to the card
until timet12 (see Fig.9). th2(ext)(rise) 1 R1-------+  V bridge hys(ext)--------------------+ ×= th2(ext)(fall) 1 R1-------+  V bridge hys(ext)--------------------– ×= S1 S2+---------------------= 0.98 R1-------× + 1 0.99
1.01----------- R1-------- 1---<×+=--- 1 1.01
0.99----------- R1-------×+< 1 1.02 R1-------× +=DD V1------->DD-------<------- 3.135
1.31--------------- 1– 0.98× 1.365=< 100 kΩ
2.365-------------------=------- 3.267
1.310--------------- 1– 0.998× 1.491=< 100 kΩ
2.49-------------------=
Philips Semiconductors Product specification
IC card interface TDA8024
8.3 Clock circuitry

The card clock signal (CLK)is derived froma clock signal
input to pin XTAL1 or from a crystal operating at up to MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL,1/2× fXTAL,1/4× fXTAL1/8× fXTAL. Frequency selection is made via
inputs CLKDIV1 and CLKDIV2 (see Table1).
Table 1
Clock frequency selection; note1
Note
The statusof pins CLKDIV1 andCLKDIV2 must notbe
changed simultaneously; a delay of 10 ns minimum
between changesis needed; the minimum durationof
any state of CLK is eight periods of XTAL1.
The frequency changeis synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the changeis
effective for only eight periods of XTAL1 after the
command.
The duty factor of fXTAL depends on the signal present at
pin XTAL1.
In order to reach a 45to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor ofto 52% and transition timesof less than 5%of the input
signal period.
If a crystal is used, the duty factor on pin CLK may beto 55% depending on the circuit layout and on the
crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
The crystal oscillator runsas soonas theICis powered up.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
cardas shownin the activationsequences shownin Figs7
and8.
If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse willbe appliedto the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
8.4 I/O transceivers

The three data lines I/O, AUX1 and AUX2 are identical.
The idle stateis realizedby bothI/O and I/OUC lines being
pulled HIGH viaa11 kΩ resistor (I/Oto VCC and I/OUCto
VDD).
Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus
allowing operation when VCC is not equal to VDD.
The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.
Aftera time delay td(edge),anN transistoron the slave side
is turned on, thus transmitting the logic 0 present on the
master side.
When the master side returnsto logic1,aP transistoron
the slave side is turned on during the time delay tpu and
then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; asshownin Fig.6,it isableto delivermore than mA at an output voltage of up to 0.9VCC into an 80pF
load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.
The current to and from the card I/O lines is limited
internallyto15 mA and the maximum frequencyon these
lines is 1 MHz.
Philips Semiconductors Product specification
IC card interface TDA8024
8.5 Inactive mode

After a Power-on reset, the circuit enters the inactive
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session: All card contacts are inactive (approximately 200 Ω to
GND) Pins I/OUC, AUX1UC and AUX2UC are in the
high-impedance state (11 kΩ pull-up resistor to VDD) Voltage generators are stopped XTAL oscillator is running Voltage supervisor is active The internal oscillator is running at its low frequency.
8.6 Activation sequence

After power-on and after the internal pulse width delay, the
system microcontroller can check the presence of a card
using the signals OFF and CMDVCCas shownin Table2.
Table 2
Card presence indication
If the card is in the reader (this is the case if PRES or
PRES is active), the system microcontroller can start a
card session by pulling CMDVCC LOW. The following
sequence then occurs (see Fig.6): CMDVCC is pulled LOW and the internal oscillator
changes to its high frequency (t0). The voltage doubler is started (between t0 and t1). VCC rises from0to5V(or3V) witha controlled slope
(t2 =t1+ 1.5×T) whereTis64 times the periodof the
internal oscillator (approximately 25 μs). I/O, AUX1 and AUX2 are enabled(t3 =t1+ 4T) (these
were pulled LOW until this moment). CLKis appliedto the C3 contactof the card reader (t4). RST is enabled (t5 =t1+ 7T).
The clock may be applied to the card using the following
sequence: Set RSTIN HIGH. Set CMDVCC LOW. Reset RSTIN LOW betweent3 andt5; CLK will startat
this moment. RST remains LOW untilt5, when RSTis enabledtobe
the copy of RSTIN. After t5, RSTIN has no further affect on CLK; this
allows a precise count of CLK pulses before toggling
RST. the applied clockis not needed, then CMDVCC maybe
set LOW with RSTIN LOW.In this case, CLK will startatt3
(minimum 200 ns after the transition on I/O), and after t5,
RSTIN may be set HIGH in order to obtain an Answer To
Request (ATR) from the card.
Activation should not be performed with RSTIN held
permanently HIGH.
Philips Semiconductors Product specification
IC card interface TDA8024
Philips Semiconductors Product specification
IC card interface TDA8024
8.7 Active mode

When the activation sequenceis completed, the TDA8024
willbeinits active mode. Datais exchanged between the
card and the microcontroller via the I/O lines. The
TDA8024 is designed for cards without VPP (the voltage
required to program or erase the internal non-volatile
memory).
8.8 Deactivation sequence

Whena sessionis completed, the microcontroller sets the
CMDVCC line HIGH. The circuit then executes an
automatic deactivation sequence by counting the
sequencer back and finishing in the inactive mode (see
Fig.9): RST goes LOW (t10). CLK is held LOW (t12 =t10+ 0.5× T) where T is64
times the period of the internal oscillator
(approximately 25 μs). I/O, AUX1 and AUX2 are pulled LOW (t13 =t10+T). VCC starts to fall towards zero (t14 =t10+ 1.5×T). The deactivation sequence is complete at tde, when
VCC reaches its inactive state. VUP falls to zero (t15 =t10+ 5T) and all card contacts
become low-impedanceto GND; I/OUC, AUX1UCand
AUX2UC remain at VDD (pulled-up via a 11 kΩ
resistor). The internal oscillator returns to its lower frequency.
Philips Semiconductors Product specification
IC card interface TDA8024
8.9 VCC generator

The VCC generator has a capacity to supply up to 80 mA
continuously at 5 V and 65 mA at 3V.
An internal overload detector operates at approximately
120 mA. Current samples to the detector are internally
filtered, allowing spurious current pulses up to 200 mA
with a duration in the order of μs to be drawn by the card
without causing deactivation. The average current must
stay below the specified maximum current value.
For reasons of VCC voltage accuracy, a 100 nF capacitor
with an ESR< 100 mΩ should be tied to CGND near to
pin VCC, anda 100or 220nF capacitor (220nFis the best
choice) with the same ESR should be tied to CGND near
card reader contact C1.
8.10 Fault detection

The following fault conditions are monitored: Short-circuit or high current on VCC Removal of a card during a transaction VDD dropping DC/DC converter operating out of the specified values
(VDDP too low or current from VUP too high) Overheating.
There are two different cases (see Fig.10): CMDVCC HIGH outside a card session. Output OFF LOWifa cardis notin the card reader, and HIGHifa
card is in the reader. A voltage drop on the VDD supply
is detected by the supply supervisor, this generates an
internal Power-on reset pulse but does not act upon
OFF. No short-circuit or overheating is detected
because the card is not powered-up. CMDVCC LOW within a card session. Output OFF
goes LOW when a fault condition is detected. As soon this occurs,an emergency deactivationis performed
automatically (see Fig.11). When the system controller
resets CMDVCC to HIGH it may sense the OFF level
again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card
extraction (OFF goes HIGH again if a card is present).
Depending on the type of card-present switch within the
connector (normally-closed or normally-open) and on the
mechanical characteristics of the switch, bouncing may
occuron the PRES signalsat card insertionor withdrawal.
There is a debounce feature in the device with an 8 ms
typical duration (see Fig.10). When a card is inserted,
output OFF goes HIGH only at the end of the debounce
time.
When the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES or PRES and output OFF goes LOW.
Philips Semiconductors Product specification
IC card interface TDA8024
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