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TDA8007B-TDA8007BHL
Multiprotocol IC card interface
1. General descriptionThe TDA8007BHL is a cost-effective card interface for dual smart card readers.
Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11,
EMV4.2 and EMV 2000. It is addressed on a non-multiplexed 8-bit databus, by means of
address registers AD0, AD1, AD2 and AD3. TDA8007BHL/C3 can be also addressed
through a multiplexed access. The integrated ISO UART and the time-out counters allow
easy use even at high baud rates with no real time constraints. Due to its chip select,
external input/output and interrupt features, it greatly simplifies the realization of a reader
of any number of cards. It gives the cards and the reader a very high level of security, due
to its special hardware against ESD, short-circuiting, power failure, etc. The integrated
step-up converter allows operation within a supply voltage range of 2.7Vto6 V.
TDA8007BHL/C4 supports only non multiplex access and TDA8007BHL/C3 support both
non multiplexed and multiplexed access.
2. Features and benefits Control and communication through an 8-bit parallel interface, compatible with
non-multiplexed memory access, TDA8007BHL/C3 can be also addressed through a
multiplexed memory access Specific ISO UART with parallel access input/output for automatic convention
processing, variable baud rate through frequency or division ratio programming, error
management at character level for T = 0 and extra guard time register FIFO for 1 to 8 characters in reception mode Parity error counter in reception mode and in transmission mode with automatic
re-transmission Dual VCC generation: 5 V ± 5 %, 65 mA (max.); 3 V ± 8 %, 50 mA (max.) or
1.8V±10 %, 30 mA (max.); with controlled rise and fall times Dual cards clock generation (up to 10 MHz), with three times synchronous frequency
doubling (fXTAL, 1 ⁄2fXTAL, 1 ⁄4fXTAL and 1 ⁄8fXTAL) Cards clock stop (at high or low level) or 1.25 MHz (from internal oscillator) for cards
Power-down mode Automatic activation and deactivation sequence through an independent sequencer Supports the asynchronous protocols T = 0 and T = 1 in accordance with:
ISO 7816 and EMV4.2 Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times
processing Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT): 22 in T = 1
and 16 in T = 0 Minimum delay between two characters in reception mode:
TDA8007BHL
Multiprotocol IC card interface
Rev. 9.1 — 18 June 2012 Product data sheet
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface– in Protocol T = 0: 11.8 ETU
– in Protocol T = 1: 10.8 ETU Supports synchronous cards Current limitations in the event of short-circuit (pins I/O1, I/O2, VCC1, VCC2, RST1
and RST2) Special circuitry for killing spikes during power-on/power-off Supply supervisor for power-on/power-off reset Step-up converter (supply voltage from 2.7 V to 6 V), doubler, tripler or follower
according to VCC and VDD Additional input/output pin allowing use of the ISO UART for another analog interface
(pin I/OAUX) Additional interrupt pin allowing detection of level toggling on an external signal (pin
INTAUX) Fast and efficient swapping between the three cards due to separate buffering of
parameters for each card Chip select input allowing use of several devices in parallel and memory space paging Enhanced ESD protections on card side (except C4x, C8x): 6 kV (min.) Software library for easy integration within the application Power-down mode for reducing current consumption when no activity.
3. Applications Multiple smart card readers for multiprocessor applications (EMV banking, digital pay
TV and access control, etc.).
4. Quick reference dataTable 1. Quick reference dataVDD = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
VDD supply voltage 2.7 - 6.0 V
VDDA analog
supply voltage
step-up converter VDD -6.0 V
IDD(pd) supply current in power-down mode cards inactive; fXTAL=0Hz - - 350 A
cards active; VCC =5V; fCLK =0 Hz; fXTAL =0Hz -- 3 mA
IDD(sm) supply current in sleep
mode
cards active; fCLK =0Hz - - 5.5 mA
IDD(oper) supply current in
operating mode
ICC1 =65mA; ICC2 =15mA; fXTAL =20 MHz;
fCLK =10 MHz; VDD =2.7V - 315 mA
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
5. Ordering informationVCC card supply output
voltage
5V card
including static loads 4.75 5.0 5.25 V
with 40 nC dynamic loads on 200 nF
capacitor
4.6 - 5.4 V
3V card
including static loads 2.78 - 3.22 V
with 24 nC dynamic loads on 200 nF
capacitor
2.75 - 3.25 V
1.8 V card
including static loads 1.65 - 1.95 V
with 12 nC dynamic loads on 200 nF
capacitor
1.62 - 1.98 V
ICC card supply output
current V card; operating - - 65 mA V card; operating - - 50 mA
1.8 V card; operating - - 30 mA
overload detection - 100 - mA
ICC1 +ICC2 sum of both card supply
output currents
operating; 5 and3 V cards - - 80 mA slew rate on VCC (rise
and fall)
CL(max)= 300nF 0.05 0.16 0.22 V/s
tdeact deactivation cycle
duration 150 s
tact activation cycle duration - 225 s
fXTAL crystal frequency 4 - 20 MHz
fext external frequency applied to pin XTAL1 0 - 20 MHz
Tamb ambient temperature 40 - +85 °C
Table 1. Quick reference data …continuedVDD = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Table 2. Ordering informationTDA8007BHL/C3 LQFP48 plastic low profile quad flat package; 48 leads; body77 1.4 mm SOT313-2
TDA8007BHL/C4 LQFP48 plastic low profile quad flat package; 48 leads; body77 1.4 mm SOT313-2
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
6. Block diagramNXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
7. Pinning information
7.1 Pinning
7.2 Pin description
Table 3. Pin descriptionRSTOUT 1 PMOS open-drain output for resetting external
devices
I/OAUX 2 input or output for an I/O line from an auxiliary smart
card interface
I/O1 3 input or output for the data line to/from card1
(ISO C7 contact)
C81 4 auxiliary I/O for ISO C8 contact (synchronous cards,
for instance) for card1
PRES1 5 card 1 presence contact input (active high)
C41 6 auxiliary I/O for ISO C4 contact (synchronous cards,
for instance) for card1
CGND1 7 ground for card 1; must be connected to GND
CLK1 8 clock output to card 1 (ISO C3 contact)
VCC1 9 card 1 supply output voltage (ISO C1 contact)
RST1 10 card 1 reset output (ISO C2 contact)
I/O2 11 input or output for the data line to/from card2
(ISO C7 contact)
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceC82 12 auxiliary I/O for ISO C8 contact (synchronous cards,
for instance) for card2
PRES2 13 card 2 presence contact input (active high)
C42 14 auxiliary I/O for ISO C4 contact (synchronous cards,
for instance) for card2
CGND2 15 ground for card 2; must be connected to GND
CLK2 16 clock output to card 2 (ISO C3 contact)
VCC2 17 card 2 supply output voltage (ISO C1 contact)
RST2 18 card 2 reset output (ISO C2 contact)
GND 19 ground
VUP 20 connection for the step-up converter capacitor;
connect a low ESR capacitor of 220 nF to AGND
SAP 21 contact 1 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SAP
and SAM
SBP 22 contact 3 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SBP
and SBM
VDDA 23 positive analog supply voltage for the step-up
converter; may be higher than VDD; decouple with a
good quality capacitor to GND
SBM 24 contact 4 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SBP
and SBM
AGND 25 analog ground for the step-up converter
SAM 26 contact 2 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SAP
and SAM
VDD 27 positive supply voltage; decouple with a good quality
capacitor to GNDtoD7 28, 29, 30, 31, 32, 33,
34, 35
input/output of data 0-7;
TDA8007BHL/C3 in case of mulitplexed
configuration: address 0-7 36 read or write selection input; high for read, low for
write 37 enable pin; same behavior as CS\ (active low) 38 chip select input (active low)
ALE 39 TDA8007BHL/C4: Not connected;
TDA8007BHL/C3: address latch enable input in
case of multiplexed configuration, connect to VDD in
non-multiplexed configuration
INT 40 NMOS interrupt output (active low)
INTAUX 41 auxiliary interrupt input
AD3 42 register selection address 3 input
AD2 43 register selection address 2 input
AD1 44 register selection address 1 input
Table 3. Pin description …continued
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8. Functional description
Remark: Throughout this document, it is assumed that the reader is familiar with ISO7816 terminology.
8.1 Interface controlThe TDA8007BHL/C3 is sensitive to ESD in functional mode. This sensitivity is seen on
pin ALE: an electrostatic discharge causes an edge on this pin and changes its mode of
communication. When the mode of communication is the multiplexed mode, this has no
impact. But when the mode used is the non-multiplexed mode, the ESD may change the
mode to multiplexed mode, which is irreversible without power-off/power-on.
The TDA8007BHL/C4 is an evolution of the C3 version in which the communication mode
is set to non-multiplexed and can not be changed.
8.1.1 Non-Multiplexed configurationThe TDA8007BHL/C4 is only in the non-multiplexed configuration (Figure 3), where the
TDA8007BHL/C3 offers a multiplexed configuration in addition to a non-mulitplexed
configuration. The configuration can be chosen through the ALE-pin. If pin ALE is tied to
VDD or ground, the TDA8007BHL/C3 will be in the non-multiplexed configuration.
The TDA8007BHL can be controlled via an 12-bit parallel bus (bits D0to D7 and bits A0 to
A3). The address bits are determined by means of pins AD0 to AD3. The read or write
control signal is on pin RD and a data write or read active low enable signal is on pin WR.
Signals CS and WR play the same role.
In read operations (see Figure 4) with signal RD = high, the data corresponding to the
chosen address is available on the bus when both signals CS and WR are low.
In write operations (see Figure 5 and 6) with signal RD = low, the data present on the bus
is written when signals CS and WR are low.
In both configurations, the TDA8007BHL/C4 is selected only when signal CS = low.
Signal INT is an active low interrupt signal.
AD0 45 register selection address 0 input
XTAL2 46 connection for an external crystal
XTAL1 47 connection for an external crystal or input for an
external clock signal
DELAY 48 connection for an external delay capacitor
Table 3. Pin description …continued
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceNXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.1.2 Multiplexed configurationThe TDA8007BHL/C3 offers a multiplexed configuration in addition to a nun multiplexed
configuration.
The TDA8007BHL/C4 does not offer the multiplexed configuration.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceIf a microcontroller with a multiplexed address and data bus (such as 80C51) is used, then
pins D0 to D7 may be directly connected to port P0 to P7, see Figure 7. Automatic
switching to the multiplexed bus configuration occurs only for TDA8007BHL/C3, if a rising
edge is detected on signal ALE.
In this event, pins AD0 to AD3 play no role and may be tied to VDD or ground.
When signal CS = low, the demulitplexing of address and data is performed internally
using signal ALE, a low pulse on pin RD allows the selected register to be read, a LOW
pulse on pin WR allows the selected register to be written to, see Figure 8. Using a 80C51
microcontroller, the TDA8007BHL/C3 is simply controlled with MOVX instructions.
8.2 Control registersThe TDA8007BHL has two complete analog interfaces which can drive cards1 and2.
The data to and from these two cards shares the same ISO UART . The data to and from a
third card (card 3), externally interfaced (with a TDA8020 or TDA8004 for example), may
also share the same ISO UART.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceCards1,2 and 3 have dedicated registers for setting the parameters of the ISO UART
(see Figure 9).
Programmable Divider Register (PDR)
Guard Time Register (GTR)
UART Configuration register 1 (UCR1)
UART Configuration Register 2 (UCR2)
Clock Configuration Register (CCR)
Cards1 and 2 also have dedicated registers for controlling their power and clock
configuration. The Power Control Register (PCR) for card 3 is controlled externally.
Register PCR is also used for writing or reading on the auxiliary card contacts C4 and C8.
Card1,2or 3 can be selected via the Card Select Register (CSR). When one card is
selected, the corresponding parameters are used by the ISO UART. Register CSR also
contains one bit for resetting the ISO UART (bit RIU= 0). This bit is reset after power-on
and must be set to logic 1 before starting with any one of the cards. It may be reset by
software when necessary.
When the specific parameters of the cards have been programmed, the UART may be
used with the following registers:
UART Receive Register (URR)
UART Transmit Register (UTR)
UART Status Register (USR)
Mixed Status Register (MSR).
In reception mode, a FIFO of 1to8 characters may be used and is configured with the
FIFO Control Register (FCR). This register is also used for the automatic re-transmission
of Not AcKnowledged (NAK) characters in transmission mode.
The Hardware Status Register (HSR) gives the status of the supply voltage, of the
hardware protections and of the card movements.
Registers HSR and USR give interrupts on pin INT when some of their bits have been
changed.
Register MSR does not give interrupts and may be used in the polling mode for some
operations; for this use, some of the interrupt sources within the registers USR and HSR
may be masked.
A 24-bit time-out counter may be started to give an interrupt after a number of ETU
programmed into the Time-Out Registers TOR1, TOR2 and TOR3. This will help the
microcontroller in processing different real-time tasks (ATR, WWT, BWT, etc.). This
counter is configured with a Time-Out counter Configuration (TOC) register. It may be
used as a 24-bit counter or as a 16-bit plus 8-bit counter. Each counter can be set to start
counting once data has been written, or on detection of a START bit on the I/O, or as
auto-reload.
xx
xx
xxx
xxx
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.2.1 General registers
8.2.1.1 Card select registerThe Card Select Register (CSR) is used for selecting the card on which the UART will act,
and also to reset the ISO UART.
[1] Register value at reset: all significant bits are cleared after reset, except bits CS7 to CS4 which are set to
their default value
[1] Bits SC1, SC2 and SC3 must be set at one at a time. After reset no card is selected by default
8.2.1.2 Hardware status registerThe Hardware Status Register (HSR) gives the status of the chip after a hardware
problem has been detected.
[1] Register value at reset: all significant bits are cleared after reset, except bit SUPL which is set within
pulse RSTOUT.
Table 4. Register CSR (address 00h; write and read)[1]CS7 CS6 CS5 CS4 RIU SC3 SC2 SC1
Table 5. Register CSR (address 00h; write and read)[1]7CS7
IC identifier: default value for identification the IC 0010= TDA8007BHL/C2
0011= TDA8007BHL/C3 or TDA8007BHL/C46CS6
5CS5
4CS4
3RIU
reset ISO UART: When reset, this bit resets a large part of the UART registers to their initial value. Bit RIU must be reset before any
activation; logic 0 for at least 10 ns duration. Bit RIU must be set to
logic 1 by software before any action on the UART can take place.
2SC3
select card 3: If bit SC3= 1, then card 3 is selected.
1SC2
select card 2: If bit SC2= 1, then card 2 is selected.
0SC1
select card 1: If bit SC1= 1, then card 1 is selected.
Table 6. Register HSR (address 0Fh; read only)[1]HS7 PRTL2 PRTL1 SUPL PRL2 PRL1 INTAUXL PTL
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceWhen at least one of the bits PRTL2, PRTL1, PRL2, PRL1 or PTL is high, then INT is low.
The bits having caused the interrupt are cleared when register HSR has been read-out.
The same occurs with INTAUXL, if not disabled.
In case of an emergency deactivation (by bits PRTL2, PRTL1, SUPL, PRL2, PRL1 PTL), bit START (bit 0 in the PCR) is automatically reset by hardware.
At power-on, or after a supply voltage drop-out, bit SUPL is set and pin INT = low. Pin INT
will return to high level at the end of the alarm pulse RSTOUT (see Figure3).
Bit SUPL will be reset only after a status register read-out outside the alarm pulse.
A minimum time of 2 µs is needed between two successive read operations of
register HSR, as well as between reading of register HSR and activation (write in
register PCR).
8.2.1.3 Time-out registersThe three Time-Out Registers (TOR1, TOR2 and TOR3) form a programmable 24-bit ETU
counter, or two independent counters (one 16-bit and one 8-bit). The value to load in
registers TOR1, TOR2 and TOR3 is the number of ETU to count. The time-out counters
may only be used when a card is active with a running clock.
[1] Register value at reset: all bits are cleared after reset.
[1] Register value at reset: all bits are cleared after reset.
Table 7. Description of HSR bits HS7 not used
6PRTL2
protection 2: Bit PRTL2= 1 when a fault has been detected on card
reader 2. Bit PRTL 2 is the OR-function of the protection on pin VCC2
and pin RST2.
5PRTL1
protection 1:. Bit PRTL1= 1 when a fault has been detected on card
reader 1. Bit PRTL 1 is the OR-function of the protection on pin VCC1
and pin RST1.
4SUPL
supervisor latch. Bit SUPL= 1 when the supervisor has been
activated.
3PRL2
presence latch 2: Bit PRL2= 1 when a level change has occurred on
pin PRES2.
2PRL1
presence latch 1: Bit PRL1= 1 when a level change has occurred on
pin PRES1. INTAUXL
auxiliary interrupt change: Bit INTAUXL= 1 if the level on
pin INTAUX has been changed.
0PTL
overheating: Bit PTL= 1 if overheating has occurred.
Table 8. Register TOR1 (address 09H; write only)[1]TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0
Table 9. Register TOR2 (address 0AH; write only)[1]TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface[1] Register value at reset: all bits are cleared after reset.
8.2.1.4 Time-out configuration registerThe Time-Out Configuration (TOC) register is used for setting different configurations of
the time-out counter as given in Table 11; all other configurations are undefined.
[1] Register value at reset: all bits are cleared after reset.
Table 10. Register TOR3 (address 0Bh; write only)[1]TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16
Table 11. Register TOC (address 0Bh; read and write)[1]TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0
Table 12. Card registers (address 00h to F5h00H All counters are stopped.
05H Counters 2 and 3 are stopped; counter 1 continues to operate in auto-reload mode.
61H Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value
stored in registers TOR3 and TOR2 is started after 61H is written in register TOC. An
interrupt is given, and bit TO3 is set within register USR when the terminal count is
reached. The counter is stopped by writing 00H in register TOC, and should be
stopped before reloading new values in registers TOR2 and TOR3.
65H Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.
Counter 1 starts counting the content of register TOR1 on the first START bit
(reception or transmission) detected on pin I/O after 65H is written in register TOC.
When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
register USR is set, and the counter automatically restarts the same count until it is
stopped. It is not allowed to change the content of register TOR1 during a count.
Counters 3 and 2 are wired as a single 16-bit counter and start counting the value in
registers TOR3 and TOR2 when 65H is written in register TOC. When the counter
reaches its terminal count, an interrupt is given and bit TO3 is set within register USR.
Both counters are stopped when 00H is written in register TOC. Counters 3 and2
shall be stopped by writing 05H in register TOC before reloading new values in
registers TOR2 and TOR3.
68H Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in
registers TOR3, TOR2 and TOR1 is started after 68H is written in register TOC. The
counter is stopped by writing 00H in register TOC. It is not allowed to change the
content of registers TOR3, TOR2 and TOR1 within a count.
71H Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value
stored in registers TOR3 and TOR2 and is started on the first START bit detected on
pin I/O (reception or transmission) after the value has been written, and then on each
subsequent START bit. It is possible to change the content of registers TOR3 and
TOR2 during a count; the current count will not be affected and the new count value
will be taken into account at the next START bit. The counter is stopped by writing
00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1 must not
be all zero.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceThe time-out counter is very useful for processing the clock counting during ATR, the
Work Waiting Time (WWT) or the waiting times defined in protocol T= 1. It should be
noted that the 200 and nmax clock counter (nmax= 368 for TDA8007BHL/C4) used during
ATR is done by hardware when the start session is set, specific hardware controls the
functionality of BGT in T= 1 and T= 0 protocols and a specific register is available for
processing the extra guard time.
Writing to register TOC is not allowed as long as the card is not activated with a running
clock.
Before restarting the 16-bit counter (counters3 and 2) by writing 61H, 65H, 71H, 75H,
F1H or F5H in the TOC; or the 24-bit counter (counters 3, 2 and 1) by writing 68H in the
TOC; it is mandatory to stop them by writing 00h in the TOC.
Detailed examples of how to use these specific timers can be found in application note
“AN01054”.
75H Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.
Counter 1 starts counting the content of register TOR1 on the first START bit
(reception or transmission) detected on pin I/O after 75H is written in register TOC.
When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
register USR is set, and the counter automatically restarts the same count until it is
stopped. Changing the content of register TOR1 during a count is not allowed.
Counting the value stored in registers TOR3 and TOR2 is started on the first START
bit detected on pin I/O (reception or transmission) after the value has been written,
and then on each subsequent START bit. It is possible to change the content of
registers TOR3 and TOR2 during a count; the current count will not be affected and
the new count value will be taken into account at the next START bit. The counter is
stopped by writing 00H in register TOC. In this configuration, registers TOR3, TOR2
and TOR1 must not be all zero.
7CH Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in
registers TOR3, TOR2 and TOR1 is started on the first START bit detected on pin I/O
(reception or transmission) after the value has been written, and then on each
subsequent START bit. It is possible to change the content of registers TOR3, TOR2
and TOR1 during a count; the current count will not be affected and the new count
value will be taken into account at the next START bit. The counter is stopped by
writing 00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1
must not be all zero.
85H Same as value 05H, except that all the counters will be stopped at the end of the 12th
ETU following the first received START bit detected after 85H has been written in
register TOC.
E5H Same configuration as value 65H, except that counter 1 will be stopped at the end of
the 12th ETU following the first START bit detected after E5H has been written in
register TOC.
F1H Same configuration as value 71H, except that the 16-bit counter will be stopped at the
end of the 12th ETU following the first START bit detected after F1H has been written
in register TOC.
F5H Same configuration as value 75H, except the two counters will be stopped at the end
of the 12th ETU following the first START bit detected after F5H has been written in
register TOC.
Table 12. Card registers (address 00h to F5h …continued
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.2.2 ISO UART registers
8.2.2.1 UART Transmit Register (UTR)[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to transmit a character to the selected card, it writes the
data in direct convention in the UART transmit register. The transmission:
Starts at the end of writing (on the rising edge of signal WR\) if the previous character
has been transmitted and if the extra guard time has expired
Starts at the end of the extra guard time if this one has not expired
Does not start if the transmission of the previous character is not completed
With a synchronous card (bit SAN within register UCR2 is set), only signal D0 is
relevant and is copied on pin I/O of the selected card.
8.2.2.2 UART Receive Register (URR)[1] Register value at reset: all bits are cleared after reset.
When the microcontroller wants to read data from the card, it reads it from the UART
Receive Register (URR) in direct convention:
With a synchronous card, only D0 is relevant and is a copy of the state of the selected
card I/O
When needed, this register may be tied to a FIFO whose length ‘n’ is programmable
between 1 and 8; if n >1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
With a parity error: _ In protocol T= 0; the received byte is not stored in the FIFO and the error
counter is incremented. The error counter is programmable between 1 and8.
When the programmed number is reached, then the bit PE is set in the status
register USR and INT0 falls low. The error counter must be reprogrammed to the
desired value after its count has been reached _In protocol T= 1; the character is loaded in the FIFO and the bit PE is set
whatever the programmed value in the parity error counter
When the FIFO is full, then the bit RBF in the status register USR is set. This bit is
reset when at least one character has been read from URR
When the FIFO is empty, then the bit FE is set in the status register USR as long as
no character has been received.
Table 13. Register UTR (address 0DH; write only)[1]UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0
Table 14. Register URR (address 0DH; read only)[1]UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.2.2.3 Mixed Status Register (MSR)The MSR relates the status of pin INTAUX, the cards presence contacts PRES1
and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive
ready indicator TBE/RBF. It also gives useful indications when switching the clock to or
from 1/2 fint and when driving the TDA8007BHL/C4 with fast controllers.
No bits within register MSR act upon signal INT.
[1] Register value at reset: bits TBE/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set
after reset.
Table 15. Register MSR (address 0Ch; read only)[1]CLKSW FE BGT CRED PR2 PR1 INTAUX TBE/RBF
Table 16. Description of MSR bits CLKSW
clock switch: Bit CLKSW is set when the TDA8007BHL/C4 has
performed a required clock switch from 1⁄nfXTAL to ⁄2fint, and is reset
when the TDA8007BHL/C4 has performed a required clock switch from
1⁄2fint to 1⁄n fXTAL. The application must wait until this bit is set or reset
before sending a new command to the card. This bit is reset at power-on.
6FE
FIFO Empty: Bit FE is set when the reception FIFO is empty. It is reset
when at least one character has been loaded in the FIFO.
5BGT
block guard time: In protocol T= 1, bit BGT is linked with a 22-ETU
counter which is started at every START bit on pin I/O. Bit BGT is set if the count is finished before the next START bit. This helps to verify that
the card has not answered before 22 ETU after the last transmitted
character, or that the reader is not transmitting a character before 22 ETU after the last received character.
In protocol T= 0, bit BGT is linked with a 16-ETU counter which is
started at every START bit on pin I/O. Bit BGT is set if the count is finished before the next START bit. This helps to verify that the reader
is not transmitting a character before 16 ETU after the last received
character. CRED
control ready: It is advised bit CRED is used for driving the TDA8007BHL/C4 with high speed controllers. Before writing in
registers TOC or UTR, or reading from register URR, check if bit CRED
is set. If reset, it means that the writing or reading operation will not be correct because the controller is acting faster than the required time for
this operation:
3PR2
card 2 present: Bit PR2= 1 when card 2 is present.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface2PR1
card 1 present. Bit PR1= 1 when card 1 is present.
1INTAUX
auxiliary interrupt. Bit INTAUX is set when pin INTAUX= high and it is
reset when pin INTAUX= low.
0TBE/RBF
transmit buffer empty/receive buffer full. Bit TBE/RBF= 1 when:
- changing from reception mode to transmission mode
- the reception FIFO is full.
- a character has been transmitted by the UART
Bit TBE/RBF= 0 after power-on or after one of the following:
- when bit RIU is reset
- when a character has been written to register UTR
- when at least one character has been read in the FIFO
- when changing from transmission mode to reception mode.
Table 16. Description of MSR bits …continued
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceNXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceNXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.2.2.4 FIFO Control Registers (FSR)The FCR relates the parity error count and the FIFO length.
[1] Register value at reset: all relevant bits are cleared after reset.
8.2.2.5 UART Status Register (USR)The USR is used by the microcontroller to monitor the activity of the ISO UART and that of
the time-out counter. If any of the status bits FER, OVR, PE, EA, TO1, TO2 or TO3 are
set, then signal INT= low. The bit having caused the interrupt is reset 2 ms after the rising
edge of signal RD during a read operation of register USR.
If bit TBE/RBF is set and if the mask bit DISTBE/RBF within register UCR2 is not set, then
also signal INT= low. Bit TBE/RBF is reset 3 clock cycles after data has been written in
register UTR, or 3 clock cycles after data has been read from register URR, or when
changing from transmission mode to reception mode.
In order to avoid counting these clock cycles, bit CRED (described in register MSR) may
be used.
Table 17. Register FCR (address 0Ch; write only)[1]FC7 PEC2 PEC1 PEC0 FC3 FL2 FL1 FL0
Table 18. Description of FCR bits FC7 not used
PEC2
PEC1
PEC0
Parity Error Count PEC2, PEC1 and PEC0 determine the number of allowed repetitions reception
The value 000 indicates that, if only one parity error has occurred,
bit PE is set; the value 111 indicates that bit PE will be set after 8 parity errors.
In protocol T=0:
If a correct character is received before the programmed error number is reached, the error counter will be reset
- If the programmed number of allowed parity errors is reached, bit PE
in register USR will be set as long as register USR has not been read
- If a transmitted character has been NAK by the card, then the
TDA8007BHL/C4 will automatically re-transmit it a number of times
equal to the value programmed in bits PEC2, PEC1 and PEC0; the character will be resent at 15 ETU
In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then
the automatic re-transmission is invalidated; the character manually rewritten in register UTR will start at 13.5 ETU. FC3 not used
2FL2
FIFO length. Bits FL2, FL1 and FL0 determine the depth of the FIFO:
1FL1
• 000=length1
111= length8.
0FL0
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interfaceIf LCT mode is used for transmitting the last character, then bit TBE is not set at the end of
the transmission.
[1] Register value at reset: all relevant bits are cleared after reset.
Table 19. Register USR (address 0Eh; read only)[1]TO3 TO2 TO1 EA PE OVR FER TBE/RBF
Table 20. Description of USR bits7TO3
Time-Out counter 3. Bit TO3 is set when counter 3 has reached its
terminal count.
6TO2
Time-Out counter 2. Bit TO2 is set when counter 2 has reached its
terminal count.
5TO1
Time-Out counter 1. Bit TO1 is set when counter 1 has reached its
terminal count.
4EA
Early answer is high if the first START bit on the I/O during ATR has
been detected between the first 200 and 368 clock pulses with RST low
(all activities on the I/O during the first 200 clock pulses with RST low
are not taken into account) and before the first 368 clock pulses with
RST high. These two features are re-initialized at each toggling of RST
3PE
Parity Error (PE). In protocol T= 0, bitPE= 1 if the UART has
detected a number of received characters with parity errors equal to the
number written in bits PEC2, PEC1 and PEC0 or if a transmitted
character has been NAK by the card a number of times equal to the
value programmed in bits PEC2, PEC1 and PEC0. It is set at 10.5 ETU
in the reception mode and at 11.5 ETU in the transmission mode.
In protocol T= 0, a character received with a parity error is not stored in
register FIFO (the card should repeat this character). In protocol T=1,
a character with a parity error is stored in the FIFO and the parity error
counter is not active.
2OVR
Overrun (OVR). Bit OVR= 1 if the UART has received a new character
whilst register FIFO was full. In this case, at least one character has
been lost.
1FER
Framing Error (FER). Bit FER= 1 when pin I/O was not in the high
impedance state at 10.25 ETU after a START bit. It is reset when
register USR has been read-out.
0TBE/RBF
Transmission Buffer Empty (TBE)/Reception Buffer Full (RBF). Bits TBE and RBF share the same bit within register USR: when in
transmission mode the relevant bit is TBE; when in reception mode it is
RBF.
Bit TBE= 1 when the UART is in transmission mode and when the
microcontroller may write the next character to transmit in register UTR.
It is reset when the microcontroller has written data in the transmit
register or when bit T/R within register UCR1 has been reset either
automatically or by software. After detection of a parity error in
transmission, it is necessary to wait 13.5 ETU before rewriting the
character which has been NAK by the card. (Manual mode, see
Table 18)
Bit RBF= 1 when register FIFO is full. The microcontroller may read
some of the characters in register URR, which clears bit RBF.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface
8.2.3 Card registersWhen cards 1, 2or 3 are selected, the following registers may be used for programming
some specific parameters.
8.2.3.1 Programmable Divider Register (PDR)The programmable divider registers PDR1, PDR2 and PDR3 are used for counting the
cards clock cycles forming the ETU (see Figure 16).
These are auto-reload 8-bit counters.
[1] Register value at reset: all bits are cleared after reset.
8.2.3.2 UART Configuration Registers (UCR) 2The UART configuration registers 2 UCR12, UCR22 and UCR32, relate the UART
configuration.
[1] Register value at reset: all bits are cleared after reset.
Table 21. Register PDR1,PRDR2, PDR3 (address 02h; read and write)PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Table 22. Register UCR1,UCR2, UCR3 (address 03h; read and write)[1]UC27 DISTBE/RBF DISAUX PDWN SAN AUTOCONV CKU PSC
Table 23. Description of UCR2 bits UC27 not used DISTBE/RBF
disable TBE/RBF interrupt bit. If bit DISTBE/RBF= 1, then reception
or transmission of a character will not generate an interrupt. This
feature is useful for increasing communication speed with the card; in
this case, a copy of the bit TBE/RBF within register MSR must be
polled (and not the original) in order not to lose priority interrupts which
can occur in register USR. DISAUX
disable auxiliary interrupt. If bit DISAUX in register UCR2 is set, then
a change on pin INTAUX will not generate an interrupt, but bit INTAUXL
will be set. Therefore, it is necessary to read register HSR before
bit DISAUX is to be reset to avoid an interrupt by bit INTAUXL. In order
to avoid an interrupt during a change of card, it is better to set
bit DISAUX in register UCR2 for all cards.
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface4PDWN
power-down mode. If bit PDWN is set by software, the crystal
oscillator is stopped. This mode allows low power consumption in
applications where this is required. During the Power-down mode, it is
not possible to select a card other than the one currently selected.
There are five ways of escaping from the Power-down mode:
- withdraw card 1 or 2
- Select the TDA8007BHL/C4 by resetting bit CS (this assumes that
the TDA8007BHL/C4 had been deselected after setting Power-down
mode)
- insert card1or card2
- Bit INTAUXL has been set due to a change on pin INTAUX
- If pin CS = low permanently, reset bit PDWN by software.
After any of these events, the TDA8007BHL/C4 will leave the
Power-down mode.
Except in the case of a read operation of register HSR, signal INT will
be pulled to low level. The system microcontroller may then read the
status registers after 5 ms, and signal INT will return to high level (if the
system microcontroller has woken the TDA8007BHL/C4 by re-selecting
it, then no bits will be set in the status registers).
Note that the Power-down mode can only be entered if bit SUPL has
been cleared. SAN
synchronous/asynchronous card. Bit SAN= 1 by software if a
synchronous card is expected. The UART is then bypassed and only
bit 0 in registers URR and UTR is connected to pin I/O. In this case the
clock is controlled by bit SC in register CCR. AUTOCONV
auto convention. If bit AUTOCONV= 1, then the convention is set by
software using bit CONV in register UCR1. If the bit is reset, then the
configuration is automatically detected on the first received character
whilst the start session (bit SS) is set.
Bit AUTOCONV must not be changed during a card session.
1CKU
clock UART. For baud rates other than those given in Table 24, there is
the possibility to set bit CKU= 1. In this case, the ETU will last half the
number of card clock cycles equal to prescaler PDRx. Note that
bit CKU= 1 has no effect if fCLK = fXTAL. This means, for example, that
76800 baud is not possible when the card is clocked with the external
frequency on pin XTAL1. PSC
prescale Select. If bit PSC= 1, then the prescaler value is 32. If
bit PSC= 0, then the prescaler value is 31. One ETU will last a number
of cards clock cycles equal to prescaler PDRx. All baud rates specified
in the ISO 7816 norm are achievable with this configuration (see
Table 24).
Table 23. Description of UCR2 bits
NXP Semiconductors TDA8007BHL
Multiprotocol IC card interface[1] Example: 31;12 in the table means prescaler set to 31 and PDR set to 12
8.2.3.3 Guard Time Registers (GTR)The guard time registers GTR1, GTR2 and GTR3 are used for storing the number of
guard ETU given by the card during ATR. In transmission mode, the UART will wait this
number of ETU before transmitting the character stored in register UTR.
When register GTRx= FF:
In protocol T=1
TDA8007BHL/C4 operates at 10.8 ETU
In protocol T=0
TDA8007BHL/C4 operates at 11.8 ETU.
[1] Register value at reset: all bits are cleared after reset.
8.2.3.4 UART Configuration Registers (UCR) 1The UART configuration registers 1 (UCR11, UCR21 and UCR31) set the parameters of
the ISO UART.
[1] Register value at reset: all bits are cleared after reset.
Table 24. Baud rate selection using values F and D[1]PSC= 31: fCLK = 3.58 MHz; PSC= 32: fCLK = 4.92 MHz 31;12
31;12
31;18
31;24
31;36
31;48
31;60
32;16
32;24
32;32
32;48
32;64
2400 31;6
31;6
31;9
31;12
31;18
31;24
31;30
32;8
32;12
32;16
32;24
32;32
4800 31;3
31;3
31;6
31;9
31;12
31;15
32;4
32;6
32;8
32;12
32;16
9600 31;3
31;6
32;2
32;3
32;4
32;6
32;8
19200 31;3
32;1
32;2
32;3
32;4
38400 32;1
32;2
76800 31;1
31;1
31;2
31;3
31;4
31;5
32;2
32;4
931;3
Table 25. Register GTR1, GTR2, GTR3 (address 05H; read and write)[1]
GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0
Table 26. Register UCR11, UCR21 and UCR31 (address 06H; read and write)[1]UC17 FIP FC PROT T/R LCT SS CONV
