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TDA7467-TDA7467D
AUDIO MATRIX WITH SRS EFFECTS
TDA7467AUDIO MATRIX WITH SRS EFFECTS
1 STEREO INPUT
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
- MUTE FUNCTION
MONO MODE (SRS 3D MONO)
STEREO MODE (SRS 3D STEREO)
SPACE AND CENTER ATTENUATORS ARE
AVAILABLE
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS (I2 C BUS)
DESCRIPTIONThe TDA7467 is a SRS (Sound Retrieval System)
audio matrix. It reproduces SRS sound process-
ing stereo and mono sources both.
The SRS sound is guaranteed by external com-
ponents and it is not affected by internal process
spreads.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers according to the SRS labs specifica-
tion.
Control of all the functions is accomplished by serial
bus. Thanks to the used BIPOLAR/CMOS/DMOS
technology, Low Distortion, Low Noise and DC
stepping are obtained.
The Device incorporates the SRS
(Sound Retrieval System) under
licence from SRS Labs, Inc.
PIN CONNECTION (Top view)
BLOCK DIAGRAM
TDA74672/11
THERMAL DATA
QUICK REFERENCE DATA
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,
Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
SUPPLY
TDA7467
ELECTRICAL CHARACTERISTICS (continued)AUDIO OUTPUTS
SRS SURROUND SOUND MATRIX
TDA74674/11
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7467 and viceversa takes place through the
2 wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte FormatEvery byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7467
SOFTWARE SPECIFICATIONInterface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte
A subaddress bytes
A sequence of data (N byte + achnowledge)
A stop condition (P)
CHIP ADDRESS SUBADDRESS DATA 1 to DATA nMSB LSB MSB LSB MSB LSB
ACK = Achnowledge
S = Start
P = Stop
B = Auto Increment
EXAMPLES
No Incremental BusThe TDA7467 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no in-
cremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Incremental BusThe TDA7467 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incre-
mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBAD-
DRESS from "1XXXX1XX" to "1XXX1111" of DATA are ignored.
The DATA 1 concerns the subaddress sent, and the DATA 2 concerns the subaddress plus one sent in
the loop etc. and at the end, it receives the stop condition.
CHIP ADDRESS SUBADDRESS DATAMSB LSB MSB LSB MSB LSB
CHIP ADDRESS SUBADDRESS DATA 1 to DATA nMSB LSB MSB LSB MSB LSB
TDA74676/11
