TDA7449L Fast Delivery |IC PHOENIX CO.,LIMITED

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TDA7449L
LOW COST DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7449L
LOW COST
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- 2 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7449L is a volume control and balance
(Left/Right) processor for quality audio applica-
tions in TV systems.
Selectable input gain is provided. Control of all
the functions is accomplished by serial bus.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
QUICK REFERENCE DATA
TDA7449L
2/13
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ,
RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified)
SUPPLY
TDA7449L
3/13
ELECTRICAL CHARACTERISTICS (continued.)
TEST CIRCUIT
APPLICATION SUGGESTIONS
The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7449L audioprocessor provides 2 bands
tones control.
CREF
The suggested 10μF reference capacitor (CREF)
value can be reduced to 4.7μF if the application
requires faster power ON.
TDA7449L
4/13
Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD
Figure 4: Channel separation vs. frequency
TDA7449L
5/13
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7449L and vice versa takes place through
the 2 wires I2 C BUS interface, consisting of the
two lines SDA and SCL (pull-up resistors to posi-
tive supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audio processor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audio processor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio
processor, the μP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 3: Data Validity on the I2 CBUS
Figure 4: Timing Diagram of I2 CBUS
Figure 5: Acknowledge on the I2 CBUS
TDA7449L
6/13
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7449L
address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU420
SUBADDRESS DATA 1 to DATA n
EXAMPLES
No Incremental Bus
The TDA7449L receives a start condition, the cor-
rect chip address, a subaddress with the B = 0
(no incremental bus), N-data (all these data con-
cern the subaddress selected), a stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU421
SUBADDRESS DATA
Incremental Bus
The TDA7449L receive a start conditions, the
correct chip address, a subaddress with the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of
DATA are ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
MSB LSB MSB LSB MSB LSB
CHIP ADDRESS
D96AU422
SUBADDRESS DATA 1 to DATA n
TDA7449L
7/13

Partno	Mfg	Dc	Qty	Available	Descript
TDA7449L	ST ?	N/a	80	avai	LOW COST DIGITALLY CONTROLLED AUDIO PROCESSOR