TDA7430TR Fast Delivery |IC PHOENIX CO.,LIMITED

TDA7430TR ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERAbsolute Maximum RatingsSymbol Parameter Value UnitV Operating Supply Voltage 11 VST Operating Ambi ..
TDA7431 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERBLOCK DIAGRAM (TDA7430)2/212.7K 5.6K5.6nF 18nF 22nF 100nF 100nF5.6nF 680nF 100nF 4.7nF 22nF 22nF2.2 ..
TDA7431 ,DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLERapplications in- AVAILABILITY OF LOUDSPEAKERcar radio and Hi-Fi systems. EQUALIZATION FIXED BY EXT ..
TDA7432 ,BASIC FUNCTION AUDIO PROCESSORELECTRICAL CHARACTERISTICS (T = 25°C, V = 9V, R = 10kΩ, R = 50Ω,amb S L gall variable gains = 0dB, ..
TDA7433D ,BASIC FUNCTION AUDIO PROCESSORELECTRICAL CHARACTERISTICS (T = 25°C, V = 9V, R = 10kΩ, R = 50Ω,amb S L gall variable gains = 0dB, ..
TDA7433D ,BASIC FUNCTION AUDIO PROCESSORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Operating Supply Voltage 10.2 VSTamb Operating ..
THS0842 ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownblock diagramAVDDDRV DVDD DDCOUTCLK Timing CircuitryCOUTI +Sample& HoldI –DA(7–0)3-State8 BITBUSMUX ..
THS0842IPFB ,8-Bit, 40 MSPS ADC Dual Ch. (Config.), Dual Simultaneous S&H, Low Power, PowerDownTHS0842 DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTERWITH SINGLE OR DUAL PARALLE ..
THS10064 ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerFEATURES DESCRIPTION* High-Speed 6 MSPS ADCThe THS10064 is a CMOS, low-power, 10-bit, 6 MSPS* 4 Ana ..
THS10064CDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTHS10064DGND to D ..
THS10064CDAR ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low PowerELECTRICAL CHARACTERISTICS over recommended operating conditions, AV = 5 V, DV = BV = 3.3 V, f = ..
THS10064IDA ,10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Powermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..

TDA7430TR
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER
1/23
TDA7430
TDA7431
June 2004
1FEATURES 1 STEREO (4STEREO) INPUT + 1 MIXER
INPUT INPUT ATTENUATION CONTROL IN 0.5dB
STEP VOICE CANCELLER IS AVAILABLE TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE
AVAILABLE MUSIC: 4 SELECTABLE RESPONSES MOVIE AND SIMULATED:
256 SELECTABLE RESPONSES 2 SPEAKERS AND 2 RECORD
ATTENUATORS: 2 INDEPENDENT SPEAKERS AND 2 INDE-
PENDENT RECORD CONTROL
IN 1dB STEP FOR BALANCE FACILITY AVAILABILITY OF LOUDSPEAKER EQUAL-
IZATION FIXED BY EXTERNAL COMPO-
NENTS INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS DESCRIPTION
The TDA7430/TDA7431 is volume tone (bass middle
and treble) balance (Left/Right) processors voice
canceller for quality audio applications in car radio
and Hi-Fi systems.
They reproduce surround sound by using pro-
grammable phase shifters and a signal matrix.
Control of all the functions is accomplished by se-
rial bus. The AC signal setting is obtained by resis-
tor networks and switches combined with
operational amplifiers. Thanks to the used BIPO-
LAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH
SURROUND SOUND MATRIX AND VOICE CANCELLER
Figure 2. Pin Connection (TDA7430)
REV. 10
TDA7430 - TDA7431
Figure 3. Pin Connection (TDA7431)
Table 2. Absolute Maximum Ratings
Table 3. Quick Reference Data
Table 4. Thermal Data
3/23
TDA7430 - TDA7431
Figure 4. TEST CIRCUIT (TDA7430)
Figure 5. TEST CIRCUIT (TDA7431)
TDA7430 - TDA7431
Figure 6. Block Diagram (TDA7430)
5/23
TDA7430 - TDA7431
Figure 7. Block Diagram (TDA7431)
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms;
RG = 600Ω, all controls flat (G = 0dB), Effect CTRL = -6dB, MODE = OFF; f = 1KHz unless otherwise
specified).
7/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (continued)
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (continued)
9/23
TDA7430 - TDA74312 C BUS INTERFACE
Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2
wires I2 C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
3.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Table 5. Electrical Characteristcs (continued)
TDA7430 - TDA7431
Figure 8. Data validity on the I2 C bus
Figure 9. Timing Diagram of I2 C bus
Figure 10. Acknowledge on the I2 C bus SOFTWARE SPECIFICATION
4.1 Interface Protocol
The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7430/TDA7431 address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)
Figure 11.
11/23
TDA7430 - TDA7431 EXAMPLES
5.1 No Incremental Bus
The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no
incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
Figure 12.
5.2 Incremental Bus
The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 1
(incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA
2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
Figure 13. DATA BYTES
Address = 80(HEX) ADDR open; 82 (HEX): need to connect supply
6.1 Function Selection
Table 6. The first byte (Subaddress)
B = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferent 0,1
TDA7430 - TDA7431
Table 7. INPUT ATTENUATION SELECTION
INPUT ATTENUATION = 0 ~ -31.5dB
Table 8.

Partno	Mfg	Dc	Qty	Available	Descript
TDA7430TR	ST	N/a	986	avai	DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER