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TDA7342N-TDA7342NTR
DIGITALLY CONTROLLED AUDIO PROCESSOR
TDA7342DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- TWO STEREO AND ONE MONO INPUTS
- ONE QUASI DIFFERENTIAL INPUT
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
FULLY PROGRAMMABLE LOUDNESS
FUNCTION
VOLUME CONTROL IN 0.3dB STEPS IN-
CLUDING GAIN UP TO 20dB
ZERO CROSSING MUTE, SOFT MUTE AND
DIRECT MUTE
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1.25dB STEPS FOR
BALANCE AND FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTIONThe audioprocessor TDA7342 is an upgrade of
the TDA731X audioprocessor family.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are imple-
mented.
The soft Mute function can be activated in two
ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 21 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
BLOCK DIAGRAM
TDA73422/14
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
QUICK REFERENCE DATA
PIN CONNECTION
TDA73423/14
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB;f = 1KHz. Refer to the test circuit, unless otherwise specified.)
INPUT SELECTOR
DIFFERENTIAL INPUT ( IN 3)
VOLUME CONTROL
LOUDNESS CONTROL
TDA73424/14
ELECTRICAL CHARACTERISTICS (continued.)
ZERO CROSSING MUTE
SOFT MUTE
BASS CONTROL
TREBLE CONTROL
SPEAKER ATTENUATORS
AUDIO OUTPUT
TDA73425/14
ELECTRICAL CHARACTERISTICS (continued)
BUS INPUTSNote 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
TDA73426/14
Figure 4: Timing Diagram of I2 CBUS
Figure 3: Data Validity on the I2 CBUS
2 C BUS INTERFACEData transmission from microprocessor to the
TDA7342 and viceversa takes place thru the 2
wires I2 C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data ValidityAs shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte FormatEvery byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
AcknowledgeThe master (μP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without AcknowledgeAvoiding to detect the acknowledge of the audio-
processor, the μP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5: Acknowledge on the I2 CBUS
TDA73427/14
