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TDA3683J
Multiple voltage regulator with switch and ignition buffer
General description The TDA3683 is a multiple output voltage regulator with a power switch and anignition buffer. Several protections and diagnostic options are incorporated in this
design.
The TDA3683 is primarily developed to cover the complete power supply
requirements in car radio applications.
The standby regulators (regulators 1, 2 and 3) are especially designed to supply
digital circuitry that has to be permanently connected e.g. Controller Area Network
(CAN) bus, Digital Signal Processor (DSP) core and the microcontroller. In
combination with the reset delay capacitor (pin RDC1 or pin RDC2/3) and the reset
function (pin RST1or pin RST2/3),a proper start-up sequencefora microcontrolleris
guaranteed. The storage capacitor (pin STC) makes the standby regulator outputs
insensitive for short battery drops (e.g. during engine start-up).
The switched regulators (regulators 4, 5, 6 and 7) are intended to be used as supply
for the tuner, logic, sound processor and CD / tape control.
The power switch (pin PSW) can be used for switching the electrically powered
antenna, display unit and CD / tape drives.
The ignition buffer is intended to produce a clean logic output signal when a polluted
ignition key signal is used as input.
Features Three enable pin controlled standby regulators: REG1: 5 V / 600 mA controlled by the EN1 input REG2: 3.3 V / 200 mA controlled by the EN2/3 input REG3: 1.9 V / 150 mA controlled by the EN2/3 input Four mode pin controlled switched regulators: REG4: 8.5 V / 350 mA REG5: 5 V / 1.8 A REG6: 3.3 V / 1.2 A REG7: 2.4 V to 10 V / 2 A adjustable using external resistor divider One mode pin controlled power switch; 2.2 A continuous and 3 A surge, with delayed
lower current limit so as to be less sensitive to inrush currents One independent ignition buffer (inverted output, open-collector) with good input
protection against high transientsA storage capacitoris includedto provide back-up supplyfor the standby regulatorsin
the event of loss of battery supply
TDA3683
Multiple voltage regulator with switch and ignition buffer
Philips Semiconductors TDA3683 A hold output (3-state) which can be used to communicate to a microcontroller in the
event of an internal or external fault condition, such as: Low supply indication in Standby mode One or more switched regulators (except REG7) out of regulation Power switch output short-circuited to ground Load dump, thermal pre-warning and thermal shutdown Reset outputs (push-pull output stage) can be used to call a microcontroller in a
smooth way (adjustable delay) at the first power-up Two supply pins that can withstand load dump pulses and negative supply voltages;
the second supply pin (connected to REG5 and REG6) can be supplied from a
separate external voltage (e.g. DC-to-DC downconverter) to reduce power dissipation All regulator and power switch outputs are short-circuit proof to ground and supply
lines; the dissipationis limitedin this condition sinceall regulators (except REG3) and
power switch have a foldback current protection incorporated The TDA3683 has three modes of operation: Sleep: all outputs disabled (very low quiescent current) Standby: one or more standby regulators enabled (low quiescent current) On: all outputs enabled The standby regulators (including the reset function) and the ignition buffer also
function during load dump and thermal shutdown; the switched regulators and power
switch will be disabled during these conditions Hysteresis is incorporated on internal switching levels The TDA3683 is protected against Electrostatic Discharge (ESD) on all pins DBS23 package with low thermal resistance and flexible leads.
Quick reference data
Table 1: Quick reference data
SuppliesVP1 supply voltage1 operating 9 14.4 18 V
reverse polarity; non-operating - - 18 V
regulators 1, 2 and 3 on 4.0 14.4 50 V
jump start; t≤10 minutes - - 30 V
load dump protection; t≤50 ms;≥ 2.5 ms - 50 V
VP2 supply voltage2 operating 6.5 14.4 18 V
reverse polarity; non-operating - - 18 V
regulators 1, 2 and 3 on 0 - 50 V
jump start; t≤10 minutes - - 30 V
load dump protection; t≤50 ms;≥ 2.5 ms - 50 V
Iq(tot) total quiescent supply
current
VEN1, VEN2/3 and VMODE< 0.8V - 5 30 μA
VMODE and VIGNIN < 0.8 V;
VEN1 and VEN2/3> 2.4 V 300 450 μA junction temperature operating −40 - +150 °C
Philips Semiconductors TDA3683 Ordering information
Voltage regulator; VP = 14.4 VVo(REG1) regulator 1 output
voltage
1mA≤ IREG1≤ 600 mA 4.75 5.0 5.25 V
Vo(REG2) regulator 2 output
voltage
1mA≤ IREG2≤ 200 mA 3.15 3.3 3.45 V
Vo(REG3) regulator 3 output
voltage
1mA≤ IREG3≤ 150 mA 1.72 1.9 2.0 V
Vo(REG4) regulator 4 output
voltage
1mA≤ IREG4≤ 350 mA 8.1 8.5 8.9 V
Vo(REG5) regulator 5 output
voltage
1mA≤ IREG5≤ 1800 mA 4.75 5.0 5.25 V
Vo(REG6) regulator 6 output
voltage
1mA≤ IREG6≤ 1200 mA 3.15 3.3 3.45 V
Vo(REG7) output voltage of
regulator7
1mA≤ IREG7≤ 2000 mA Vo − 5% 2.4 to 10 Vo + 5% V
Power switchVdrop(PSW) drop-out voltage IPSW=1 A; VP1 =VP2= 13.5V - 0.45 0.65 V
IPSW= 2.2 A; VP1 =VP2= 13.5V - 1.0 1.8 V
IM(PSW) peak current VP1 =VP2 <17V 3 - - A
Table 1: Quick reference data …continued
Table 2: Ordering informationTDA3683J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA3683SD RDBS23P plastic rectangular DIL-bent-SIL (reverse bent) power package; 23 leads
(row spacing 2.54 mm)
SOT889-1
Philips Semiconductors TDA3683 Block diagram
Philips Semiconductors TDA3683 Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin descriptionVP1 1 supply voltage 1
IGNIN 2 ignition input
PSW 3 power switch output
IGNOUT 4 ignition output
HOLD 5 hold output
MODE 6 enable input for regulators 4, 5, 6, 7 and power switch
REG5 7 regulator 5 output
RST2/3 8 reset output for regulators 2 and 3
VP2 9 supply voltage 2 (for regulators 5 and 6)
RDC2/3 10 reset delay capacitor for regulators 2 and 3
REG6 11 regulator 6 output
REG3 12 regulator 3 output
Philips Semiconductors TDA3683[1] The heat tab is internally connected to pin GND.
Functional descriptionThe TDA3683isa multiple output voltage regulator witha power switch and ignition buffer.
The device is primarily intended for use in car radio applications. An overall functional
description of the building blocks is given in the following sections.
7.1 Standby regulatorsThe standby regulators (pins REG1, REG2 and REG3) are used for digital circuitry that
has to be permanently connected to a supply voltage (e.g. CAN bus DSP core or
microcontroller). REG1 is controlled by its own active HIGH enable input (EN1). REG2
and REG3 havea combined enable input (EN2/3) with similar logic properties. Permanent
voltage tracking will exist between REG2 and REG3 during power-up and power-down.All
standby regulators have a low quiescent current and will not be switched off during
thermal shutdown and load dump conditions. The outputs are protected against overload
and short-circuit conditions by a current limit / foldback protection.
7.2 Switched regulatorsThe switched regulators (pins REG4, REG5, REG6 and REG7) are activatedby the active
HIGH mode input. The regulators are protected against overload and short-circuit
conditionsbya current limit/ foldback protection. They willbe switchedoff during thermal
shutdown and load dump conditions. The output voltage of REG7 can be adjusted (2.4 V
to 10 V) by using two external resistors connected between the regulator output, the
feedback input and ground; see Figure 10. REG7 has a built-in flyback clamp for use in
case of inductive loads.
REG2 13 regulator 2 output
STC 14 storage capacitor (backup) output
REG1 15 regulator 1 output
RST1 16 reset output for regulator 1
REG4 17 regulator 4 output
RDC1 18 reset delay capacitor for regulator 1
EN1 19 enable input for regulator 1
EN2/3 20 enable input for regulators 2 and 3
REG7 21 regulator 7 output
ADJ7 22 regulator 7 adjust input
GND 23 ground / substrate[1]
Table 3: Pin description …continued
Philips Semiconductors TDA3683
7.3 Power switchThe power switch (pin PSW) is activated by the MODE input. It is switched off during
thermal shutdown and load dump conditions. The power switch output voltageis internally
clamped at 16 V to protect connected application circuitry (e.g. display and CD / tape
drives). The power switch has three different output current modes, depending on its
output voltage, the reset capacitor (RDC1) and the junction temperature (i.e. high current,
low current and foldback protection); see Figure 7. In the event of an overload the power
switch can maintain the maximum output current for a limited period of time (determined the integration timeof the reset delay capacitor) beforeit drops backto the lower output
current capability. This functionality is implemented to prevent, in case of loads such as
light bulbs, relays or electrical motors, the power switch from folding back on momentary
high inrush currents.In the eventof junction temperatures above 150 °C, the power switch
will drop backto the lower output current capability.The power switch hasa built-in flyback
clamp for use in case of inductive loads.
7.4 Enable and mode inputsThe enable inputs (pins EN1 and EN2/3) are used to switch on or switch off the standby
regulators. The mode input (MODE) is used to enable the switched regulators and the
power switch. When all of these inputs are LOW the circuit is in Sleep mode and only the
enable detection circuit and the supply overvoltage protection circuit are active. In Sleep
mode the device drawsa very small quiescent current from the supply. Whenat least one
of the enable inputs is activated the circuit will operate in Standby mode. When the mode
input is activated the on condition will be established; before the MODE pin can be
activated at least one of the standby regulators must be activated. The enable and mode
inputs are 3.3V and5V CMOS logic compatible.A detailed descriptionof the enable and
mode pin dependencies is given inT able4.
Table 4: Enable and mode pin dependencies 0 0 standby regulators, switched regulators, power switch and
ignition buffer disabled 0 1 standby regulators, switched regulators, power switch and
ignition buffer disabled 1 0 standby regulators 2 and 3 and ignition buffer enabled; standby
regulator 1, switched regulators and power switch disabled 1 1 standby regulators 2 and 3, switched regulators and ignition
buffer enabled; standby regulator 1 and power switch disabled 0 0 standby regulator 1 and ignition buffer enabled; standby
regulators 2 and 3, switched regulators and power switch
disabled 0 1 standby regulator 1, switched regulators, power switch and
ignition buffer enabled; standby regulators 2 and 3 disabled 1 0 standby regulators and ignition buffer enabled; switched
regulators and power switch disabled 1 1 standby regulators, ignition buffer, switched regulators and
power switch enabled
Philips Semiconductors TDA3683
7.5 Storage capacitorThe storage capacitor (pin STC) is used as a back-up supply for the standby regulators
when the battery (pins VP1 / VP2) can no longer provide the supply. This situation may
occur for cold weather engine starts. The rising and falling storage capacitor voltage
threshold levels determine if the standby regulators can be switched on.
The storage capacitor pinis not intendedtobe usedasan output (e.g. supply switch). No
external load should be connected to this pin.
7.6 Reset delay capacitorsThe reset delay capacitors (pins RDC1 and RDC2/3) are used to delay the reset pulse
(RST1 and RST2/3) starting from the time the associated standby regulator output voltage
comes within its regulated voltage range i.e. crosses the rising reset threshold level. An
internal current sourceis usedto charge the reset delay capacitor. The reset output willbe
released (output goes HIGH) when the voltage on the reset delay capacitor crosses the
rising threshold level. the associated standby regulator voltage drops outofits regulated voltage range (drops
below its falling reset threshold level) the reset delay capacitor will be discharged with a
relatively high sink current. The reset output willbe activated (output goes LOW) when the
reset delay capacitor crosses the falling threshold level. This featureis includedto secure smooth start-upof the microcontrollerat first connection, without uncontrolled switching
of the relevant standby regulators during a start-up sequence. It should be noted that
RDC1 is also used as a time constant for the delayed current protection of the power
switch.
7.7 Reset outputsThe reset function depends on the reset delay capacitor voltage and includes hysteresis
to avoid oscillation at the threshold level. The reset outputs are push-pull for sourcing or
sinking current. The output voltage can be switched between the ground level and the
output voltage of the relevant standby regulator. An external reset delay capacitor can be
added if a timed reset pulse is required (CRDC1 or CRDC2/3).
Standby regulator 1 has an independent reset function (pins RST1 and RDC1). Standby
regulators 2 and 3 have combined circuitry (pins RST2/3 and RDC2/3). The reset trigger
signals from both regulators are connected usingan OR functionto the reset output buffer
thus ensuring that both regulators can generate a reset when appropriate. The RST1
output is linked to standby regulator 1 (5 V) and, therefore, generates a 5 V HIGH-level
output voltage. The RST2/3 output is linked to regulator 2 (3.3 V) and, therefore,
generates a 3.3 V HIGH-level output voltage.
7.8 Hold outputThe hold output (pin HOLD) is a combined output for the thermal pre-warning signal and
all other diagnostic signals. To distinguish between these signals, the HOLD output is
designed as an active HIGH 3-state output buffer. When a no failure condition is present
the output is LOW. When a thermal pre-warning signal is generated (e.g. to shut down
other circuitsin the radio before the regulator itself shuts down) the signal risestoits MID
Philips Semiconductors TDA3683level. In all other warning situations, the HOLD output rises to its HIGH level. In order to
generate standard CMOS logic compliant signals an external decoding circuit has to be
implemented; see Figure9.
The HOLD output will be active HIGH when:
The output voltage of one or more switched regulators is out of regulation (except
REG7), due to overload or supply voltage drops
The power switch operates in the Foldback mode
In Standby or On mode the thermal shutdown is activated
In Standby or On mode the load dump protection is activated
In Standby modea low battery voltage occurs (VP1) indicating thatitis not possibleto
pull REG4 into regulation when switching it on. shouldbe noted that thereis intentionallyno out-of-regulation detectionfor REG7 since
it can be adjusted to maximum 10 V and would, in that event, activate the HOLD signal
very early.
The HOLD function includes hysteresis in order to avoid oscillations when the hold
threshold level is crossed. A schematic diagram of the HOLD function is illustrated in
Figure3.
Philips Semiconductors TDA3683
Philips Semiconductors TDA3683
7.9 Ignition bufferThe ignition buffer (pins IGNIN and IGNOUT) is an independent inverting open-collector
output buffer circuit that canbe usedto sense the start lineof the ignition keyina car. The
start line will only be pulled-up to the battery voltage in the event of an engine crank
resulting in a LOW at the inverting output of the ignition buffer. This output signal can be
used to immediately mute an audio amplifier during the engine crank. guaranteea reliable LOW output signal, evenin extreme cold weather crank conditions
(the battery voltage may momentarily drop down to 3 V) a low supply latch function is
implemented.
To make the ignition buffer input robust, for possible extreme transients present on the
battery line, an input RC filter is strongly advised. A blocking diode is also recommended
to prevent substrate injection in case of negative voltage spikes at the input.
7.10 Supply voltage inputsThe supply voltage inputs (pins VP1 and VP2) are intendedtobe connectedto the battery.
Both inputs are protected against load dump transients and reverse battery connections.
The second supply pin (VP2)is internally connectedto the high current/ low output voltage
switched regulators (REG5 and REG6) and can be connected to an external DC-to-DC
downconverter for reduced power dissipation and increased power supply efficiency.
Power mustbe appliedto pin VP1to ensure that the circuits are functional, since the band
gaps for the switched and standby regulators are connected to this supply pin.
Rising and falling supply voltage threshold levels determineif the switched regulators and
power switch can be switched on.
The timing diagrams for various regulator functions are illustrated in Figure 4 and
Figure5.
Philips Semiconductors TDA3683
Philips Semiconductors TDA3683
Philips Semiconductors TDA3683 Limiting values Thermal characteristics
10. Characteristics
Table 5: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VP1 supply voltage1 operating - 18 V
reverse polarity; non-operating - 18 V
jump start; t≤10 minutes - 30 V
load dump protection; t≤50 ms; tr≥ 2.5ms - 50 V
VP2 supply voltage2 operating - 18 V
reverse polarity; non-operating - 18 V
jump start; t≤10 minutes - 30 V
load dump protection; t≤50 ms; tr≥ 2.5ms - 50 V
Tstg storage temperature non-operating −55 +150 °C
Tamb ambient temperature operating −40 +85 °C junction temperature operating −40 +150 °C
Table 6: Thermal characteristicsRth(j-c) thermal resistance from junction to case 1 K/W
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
Table 7: CharacteristicsVP1 = VP2= 14.4 V; Tamb =25 °C; RL= ∞Ω; measured in test circuits of Figure 8; unless otherwise specified.
SuppliesVP1 supply voltage1 operating 9 14.4 18 V
regulators 1, 2 and 3 on [1] 4.0 14.4 50 V
jump start; t≤10 minutes - - 30 V
load dump protection;≤50 ms; tr≥ 2.5ms - 50 V
VP2 supply voltage2 operating 6.5 14.4 18 V
regulators 1, 2 and 3 on 0 - 50 V
jump start; t≤10 minutes - - 30 V
load dump protection;≤50 ms; tr≥ 2.5ms - 50 V
Vbat(loaddump) battery overvoltage
shutdown
VP1 and/or VP2 18 20 22 V
Philips Semiconductors TDA3683Iq(tot) total quiescent supply
current
VEN1, VEN2/3 and
VMODE< 0.8V 30 μA
VMODE and VIGNIN < 0.8 V;
VEN1 and VEN2/3 > 2.4 V 300 450 μA
VMODE and VIGNIN < 0.8 V;
VEN1 > 2.4 V; VEN2/3< 0.8V 150 250 μA
VMODE and VIGNIN < 0.8 V;
VEN1 < 0.8 V; VEN2/3> 2.4V 225 325 μA
Schmitt trigger for power supply (regulators4, 5, 6, 7 and power switch)Vth(r) rising threshold voltage VP1 and VP2 rising 6.5 7.0 7.5 V
Vth(f) falling threshold voltage VP1 and VP2 falling 4.0 4.5 5.0 V
Vhys hysteresis voltage - 2.5 - V
Schmitt trigger for enable (EN1, EN2/3) and MODE inputsVth(r) rising threshold voltage 1.4 1.8 2.4 V
Vth(f) falling threshold voltage 0.9 1.3 1.9 V
Vhys hysteresis voltage IREGx =IPSW =1mA - 0.5 - V
ILI input leakage current VENx/MODE =5V 1 5 20 μA
Reset trigger level of regulator1Vth(r) rising threshold voltage VP1 and VP2 rising;
IREG1 =50mA
[2] 4.43 VREG1− 0.15 VREG1− 0.1 V
Vth(f) falling threshold voltage VP1 and VP2 falling;
IREG1 =50mA
[2] 4.4 VREG1− 0.25 VREG1− 0.13 V
Reset trigger level of regulator2Vth(r) rising threshold voltage VP1 and VP2 rising;
IREG2 =50mA
[2] 3.03 VREG2− 0.15 VREG2− 0.1 V
Vth(f) falling threshold voltage VP1 and VP2 falling;
IREG2 =50mA
[2] 3.0 VREG2− 0.25 VREG2− 0.13 V
Reset trigger level of regulator3Vth(r) rising threshold voltage VP1 and VP2 rising;
IREG3 =50mA
[2] 1.75 VREG3− 0.10 VREG3− 0.08 V
Vth(f) falling threshold voltage VP1 and VP2 falling;
IREG3 =50mA
[2] 1.72 VREG3− 0.15 VREG3− 0.10 V
Schmitt triggers for HOLD outputVth(r)(REG4) rising threshold voltage
of regulator4
VP1 and VP2 rising [2] -VREG4− 0.15 VREG4− 0.075 V
Vth(f)(REG4) falling thresholdvoltage
of regulator4
VP1 and VP2 falling [2] 7.9 VREG4− 0.35- V
Vhys(REG4) hysteresis voltage due
to regulator4 0.2 - V
Vth(r)(REG5) rising threshold voltage
of regulator5
VP1 and VP2 rising [2] -VREG5− 0.15 VREG5− 0.075 V
Vth(f)(REG5) falling thresholdvoltage
of regulator5
VP1 and VP2 falling [2] 4.3 VREG5− 0.35- V
Table 7: Characteristics …continuedVP1 = VP2= 14.4 V; Tamb =25 °C; RL= ∞Ω; measured in test circuits of Figure 8; unless otherwise specified.
Philips Semiconductors TDA3683Vhys(REG5) hysteresis voltage due
to regulator5 0.2 - V
Vth(r)(REG6) rising threshold voltage
of regulator6
VP1 and VP2 rising [2] -VREG6− 0.15 VREG6− 0.075 V
Vth(f)(REG6) falling thresholdvoltage
of regulator6
VP1 and VP2 falling [2] 2.7 VREG6− 0.3 - V
Vhys(REG6) hysteresis voltage due
to regulator6 0.15 - V
Vth(r)(VP) rising threshold voltage
of supply voltage
VP1 and VP2 rising;
VMODE< 0.8V;
VEN1or VEN2/3 > 2.4V
7.8 8.4 9 V
Vth(f)(VP) falling thresholdvoltage
of supply voltage
VP1 and VP2 falling;
VMODE< 0.8V;
VEN1or VEN2/3 > 2.4V
7.7 8.1 8.5 V
Vhys(VP) hysteresis voltage of
supply voltage 0.3 - V
Hold bufferVo(HOLD)(L) LOW-level HOLD
output 0.1 0.6 V
Isink(L) LOW-level sink current VHOLD≤ 0.6V 0.5 - - mA
Vo(HOLD)(H) HIGH-level HOLD
output
6.0 7.0 8.0 V
Isource(H) HIGH-level source
current
VHOLD= 3.3V 1 2 - mA
Vo(HOLD)(M) MID-level HOLD output 1.8 2.15 2.5 V
Isource(M) MID-level source
current
VHOLD= 1.5V 1 2 - mA rise time CL = 50 pF - 7 50 μs fall time CL = 50 pF - 1 50 μs
Reset and Reset delay 1Isink(L) LOW-level sink current VRST1≤ 0.8V; VRDC1< 1.0V 2 - - mA
Isource(H) HIGH-level source
current
VRST1= 4.5V;
VRDC1> 3.5V
240 400 900 μA rise time CL = 50 pF - 7 50 μs fall time CL = 50 pF - 1 50 μs
Ich charge current VRDC1 =0V; VEN1 > 2.4 V 2 4 8 μA
Idch discharge current VRDC1 =3V;
VP1 =VP2= 4.3V
1.0 1.6 - mA
Vth(r)(RDC1) reset delay capacitor 1
rising voltage threshold
[3] 2.5 3.0 3.5 V
Vth(f)(RDC1) reset delay capacitor 1
falling voltage threshold
[3] 1.0 1.2 1.4 V
td(RST1) delay time reset signal CRDC1 =47nF [4] 20 35 70 ms
Table 7: Characteristics …continuedVP1 = VP2= 14.4 V; Tamb =25 °C; RL= ∞Ω; measured in test circuits of Figure 8; unless otherwise specified.
