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TC9438FN
SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES OVERSAMPLING DIGITAL FILTER/DYNAMIC DIGITAL BASS BOOST/ ANALOG FILTER
TOSHIBA
TC9438FN
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9438FN
Z-A MODULATION DA CONVERTER WITH BUILT-IN 8-TIMES
OVERSAMPLING DIGITAL FILTER/DYNAMIC DIGITAL BASS BOOST/
ANALOG FILTER
The TC9438FN is a second-order E-zl modulation system
1-bit DA converter incorporating an 8-times oversampling
digital filter, dynamic digital bass boost function for use
with compressor operations and an analog filter
developed for digital audio equipment.
Because the IC includes an analog filter, it can output a
direct analog waveform, thus reducing the size and cost
of the DA converter.
SSOP24-P-300-0.65A
Weight : 0.14g (Typ.)
In serial control mode, output amplitude can be set in 128 steps of resolution using microcontroller
FEATURES
0 Built-in 8-times oversampling digital filter
0 Low-voltage operations (2.4V) possible
It Built-in digital de-emphasis filter
0 Built-in dynamic digital bass boost function
commands
In parallel control mode, soft mute can be set for the output signal in 64 steps in 20ms
Built-in LR common digital zero detection output circuit
Sampling frequency , 44.1kHz
Supports 384fs/256fs (automatic switching)
DA converter oversampling ratio (OSR) : 192fs (at 384fs)
Stereo/monaural output selection possible
Built-in third-order analog filter
The digital filter and DA converter characteristics are shown on the next page
2001 -06-1 9
TOSHIBA
TC9438FN
Digital Filter
DIGITAL PASSBAND TRANSIENT
FILTER RIPPLE BANDWIDTH ATTENUATION
Standard Operation 8fs i0.11dB 20k--24.1kHz -26dB or less
DA Converter (VDD = 5.0V)
OSR DISTORTION S/N RATIO
192fs - 87dB (Typ.) 94dB (Typ.)
Standa d 0 e ati n
r p r IO 128fs -82dB (Typ.) 88dB (Typ.)
PIN CONNECTION BLOCK DIAGRAM
(DBB1) (EMP) (SM)
LRCK BCK DATA DBB2 ATT SHIFT LATCH v x x0 XI GNDX MCK
VDDE1 U 24EILRCK ' I
T1 E2 23 l BCK D . f Mi ll
5‘5: fig :23: “2121? ace - 142133173512 Oscillator circuit
RO E 5 2011 ATT(DBB1) 1 ' .
GNDA n 6 19 u SHIFT(EMP) . r Timing generator
VR E 7 18 l LATCH (SM) 332?!" 21°13?
GNDA E 8 17 l VDX A Digital filter circuit,
LO r 9 16 L] xo d7 de-emphasis filter circuit,
VDA E10 15 u XI attenuator circuit
ZD E 11 14 l GNDX '
GNDD E12 13 l MCK E-A modulator circuit
Test E Output - - Output E
circuit l circuit circuit l
l l l l
l Analog Analog l
T l filter - - filter l f
0) Q) L3) Q1) (5) O.) (7) O.) e.) OJ 09 Q9
VDD T1 w? l/DA RO GNDA VR GNDA LO vDA zo GNDD
2 2001-06-19
TOSHIBA TC9438FN
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTION REMARKS
1 VDD - Digital block power supply pin
2 T1 I Test pin. Always set to "Low" level.
3 P/T; I Parallel/serial mode select pin
4 VDA - Analog power supply pin
5 RO C) Right channel analog signal output pin
6 GNDA - Analog GND pin
7 VR - Reference voltage pin
8 GNDA - Analog GND pin
9 LO O Left channel analog signal output pin
10 VDA - Analog power supply pin
11 2D 0 Zero data detection output pin common to left and right
channels
12 GNDD - Digital GND pin
13 MCK o System clock output pin
14 GNDX - Crystal oscillator GND pin
15 XI I Crystal oscillator connecting pins. -Elifii3,
16 XO 0 Generate the clock required by the system. XI XO
17 VDX - Crystal oscillator power supply pin
18 LATCH I In serial mode, data latch signal input pin Schmidt
(SM) In parallel mode, soft mute control pin input
19 SHIFT I In serial mode, shift clock input pin Schmidt
(EMP) In parallel mode, de-emphasis filter control pin input
20 ATT I In serial mode, data input pin Schmidt
(DBB1) In parallel mode, dynamic bass boost control pin 1 input
21 DBB2 I In parallel mode, dynamic bass boost control pin 2
22 DATA I Audio data input pin thmldt
23 BCK I Bit clock input pin Sshmldt
24 LRCK I LR clock input pin S.chmift
3 2001-06-19
TOSHIBA TC9438FN
DESCRIPTION OF BLOCK OPERATIONS
1. Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as
shown in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin
(pin 15). However, in this situation, due consideration must be given to the fact that waveform
characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect
the DA converter's noise distortion and the S/N ratio.
To internal circuit
-il) (l)"?),
GNDX XI xo VDX MCK
ll 16.9344MH2
E lCL CL--10-33PF
Use a crystal with a low CI value and favorable start-up characteristics.
Fig.1 Crystal Oscillator Circuit Configuration (when in the 384fs mode)
The timing generator generates the clocks and process timing signals required for such functions as
digital filtering and de-emphasis filtering.
2. Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is
consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK
signal falling edge as indicated in the timing example below. Also, as DATA has been designed so
that the 16 bits before the change point of LRCK are regarded as valid data, the data must be input
with Right-justified mode when the BCK is 48fs or 64fs, as shown in Fig.2a.
LRCK -l. L-ch I !'
DATA N5415i14i13-l12-I11I1OI9‘8'7'6'5'4l3i2iLSB'VISBI15'14I13l12.11'10'9|8l7'6i5i4iBiZILSBi
Fig.2a Example of Input Timing Chart
BCK lUlllllililililalzlslllilililalalslillllllllglslslslilillllalglslilililililzlgll
Fig.2b Example of Input Timing Chart
4 2001-06-19
TOSHIBA TC9438FN
3. Digital Filter
The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth
during standard operations.
Table 1 Basic Characteristics of Digital Filter
PASSBAND TRANSIENT
SET MODE RIPPLE BANDWIDTH ATTENUATION
Standard Operations i0.11dB 20k~24.1kH2 -26dB or less
The characteristics of the digital filter frequencies are shown below.
- 10.00
- 2000
- 3000
- 40.00
- 50.00
GAIN (d B)
GAIN (d B)
- 60.00
- 70.00
- 80.00
- 9000
- - 1.
100'00 44.1 88.2 132.3 176.4 0 2.0 4.0 6.0 8.0 10.012.014.016.018.0 20.022.0 24.0
FREQUENCY (kHz) FREQUENCY (kHz)
Fig.3. Digital filter frequency characteristics
4. De-emphasis Filter
ON/OFF is controlled in the parallel mode (P/§="H") with the SHIFT (EMP) pin (pin 19).
This is set in the serial mode (P/§="L”) with a microcontroller or other equipment. (Refer to 10-2
Microcontroller setting mode for further details on serial mode settings.)
Table 2 De-emphasis Filter Settings
(when in the parallel mode)
SHIFT (EMP) PIN H L
De-emphasis Filter ON OFF
5 2001-06-19
TOSHIBA TC9438FN
The digitalization of the de-emphasis filter eliminates the need for such external components as
resistors, condensers and analog switches. In addition to this, the coefficients are aligned to reduce
error in the de-emphasis filter characteristics.
The filter structure and characteristics are shown below.
Input data
lG (Jw)|
(b +b 2'1) 1 1
Transfer function : ruz)="'0'-o"/' /TI /T2
(1-a12-1) TI=50ps, T2=15ps
Fig.4 IIR Digital De-emphasis Filter Fig.5 Filter Characteristics
5. Dynamic digital bass boost circuit
ON/OFF for the dynamic digital bass boost is controlled in the parallel mode (P/§="H") with the
DBB1 pin (pin 20) and the DBB2 pin (pin 21).
This is set in the serial mode (P/§="L”) with a microcontroller or other equipment. (Refer to 10-2
Microcontroller setting mode for further details on serial mode settings.)
A block diagram for the dynamic bass boost circuit is shown in fig.6.
fi1 OUTPUT
SERIAL
ATTENUATOR
COMPRESSOR BLOCK
Fig.6 Dynamic Digital Bass Boost Circuit Block
Coefficient length .' 7 bits
The compressor's compression ratio when in the control mode for the parallel mode is shown below.
Table 3 Compressor Compression Ratio (when in the parallel mode)
DBB MAX 18dB
DBB MID 12dB
The compressor's compression characteristics are as follows:
Table 4 Compressor compression characteristics (when in the parallel mode)
DBB MAX -36dB
DBB MID -24dit
6 2001-06-19
TOSHIBA TC9438FN
The compressor I/O characteristics for the dynamic digital bass boost are shown in fig.7.
EFS= "L"
-30 EFS="H"
COMPRESSOR GAIN OUTPUT
-100-90 -80 -70 -60 -50 -40 -30 -20 -10 0
INPUT LEVEL (dB)
Fig.7 Dynamic Digital Bass Boost Compressor I/O Characteristics
The bass boost settings when in the parallel mode are shown below.
Table 5 Bass Boost Mode Settings
MODE 1 MODE 2 MODE 3 MODE 4
DBB1 (pin 20) L L H H
DBB2 (pin 21) L H L H
MODE 1 : DBB OFF
MODE 2 : DBB MID
MODE 3 .' DBB MAX
MODE 4 : DBB MAX+HB
7 2001-06-19
TOSHIBA TC9438FN
The bus boost characteristics are shown in fig.8.
RESPONSE (dB)
20 A 20
._ _ sun
15 -- 'I V 15
0 x l tit 0 - "
1 . l 1 'ts
_ l f? - h ,
5 i, 'dl 5 ' \
' I l x” ‘Q 1: N Is te. 1
0 l l .f," 0 'k \ /.’;
tre Jk:... - 3 't JTs 9'21. .
-10 -10
0.01 0.1 1 10 100 0.01 (hl 1 10 100
FREQUENCY (kHz) FREQUENCY (kHz)
a) Vin = -36di? input, DBB OFF, 1kH2=0dB. b) Vin = -20dB input, DBB OFF, 1kH2=0dB.
Compressor characteristics
MID : EFS="L" (-24dB)
MAX : EFS="H" (-36dB)
MAGA .' EFS="H" (-36dB)
& -OFF
w 5 "".. - ..... MID
re N Is.'"-'""';
0 " x J'''' ---MAX+HB
~-\.___...»r--- "''"w, ---MEGA+HB
0.01 0.1 1 10 100
FREQUENCY (kHz)
C) Vin=0dB input, DBB OFF, 1kH2=0dB.
Compressor's compression characteristics
MID : EFS="L" (-24dB)
MAX : EFS="H" (-36dB)
MAGA .' EFS="H" (-36dB)
Fig.8 Dynamic Bass Boost Frequency Characteristics (VDD=2.7V)
8 2001-06-19
TOSHIBA TC9438FN
6. DA Conversion Circuit
The IC incorporates a second-order E-d modulation DA converter for two channels (simultaneous
output type). The internal structure of this is shown in fig.9.
. Q ( ) Output data
(Bit-stream 1-bit DA conversion data)
Second-order E-n converter : Y(Z)=X(Z)+(1-Z-1)2Q(Z)
Fig.9. E-d modulation DA converter
The E-A modulation clock has been designed to operate at 192fs (when 384fs). The noise shaping
characteristics are shown in fig.10.
NOISE POWER (d8)
0 Book IM
Frequency (Hz)
Fig.10 Noise Shaping Characteristics
7. Data output circuit
The output circuit is equipped with a third-order analog low-pass filter. This enables direct analog
signals to be acquired from the IC's RO (pin 5) and LO (pin 9) output pins.
r-NNN-q-
PDM signals-ir-ir-i-D?- R0(L0)
Fig.11 Analog Filter Circuit
9 2001-06-19
TOSHIBA
TC9438FN
8. Soft Mute Circuit
The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA
converter output by switching the SM pin (pin 18) from the "L'' level to the "H" level when in the
parallel mode (P/ff-- "H"). The soft mute's ON/OFF function and the DA converter output are
shown in fig.12.
The Soft mute ON/OFF control function is disabled during level transition.
SM pin input '
DA converter
output level I
Approximately 20ms I I Approximately 20ms
Fig.12 Changes in The Soft Mute DA Converter Output Level
9. Common left channel/right channel digital zero data detection output circuit
The IC is equipped with a common left channel/right channel digital zero data detection output
circuit, and the ZD pin (pin 11) is switched from "L'' to "H" when data for both the left channel
and the right channel becomes zero data for approximately 350ms or longer.
This is fixed at "L" when the data for the left channel and right channel is not zero data.
10.Description of internal control signals
The p/T pin can be used to switch between the parallel mode (P/T pin="H" in DC setting mode)
and the serial mode (P/T pin ="L" with the microcontroller interface function).
10-1 Parallel mode (p/T="H" : DC setting mode)
Pins 18, 19, 20 and 21 are used as the mode setting pins shown in the table below when in
the parallel mode.
Table 6 Pin Names at The Parallel Mode
PIN No. PIN NAME PIN DESCRIPTION
18 SM Soft mute control pin
19 EMP De-emphasis control pin
20 DBBI Digital bass boost mode control pin 1
21 D332 Digital bass boost mode control pin 2
2001 -06-1 9
TOSHIBA TC9438FN
10-2 Serial mode (P/T='l" : Microcontroller setting mode)
It is possible to make the various settings with a microcontroller when in the serial mode.
Pins 18, 19 and 20 are used as the command input pins shown in the table below when in
the serial mode.
Table 7 Pin Names at The Serial Mode
PIN No. PIN NAME PIN DESCRIPTION
18 LATCH Data latch signal input pin
19 SHIFT Shift clock signal input pin
20 ATT Data input pin
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT
signal rising edge. It is consequently necessary for the data input from the ATT pin on the
shift signal rising edge to be valid as indicated in the timing example in fig.13. It is also
necessary for the LATCH pulse to rise at least 1.5,as after the final clock rising edge input
from the SHIFT pin. Operating the shift clock with LATCH low destabilizes the internal state,
which may lead to malfunctions, so it must therefore be set to the low level after loading D7
to the register.
LATCH ct
srnrTiiititititititit
ATT IDO I D1 I D2 I D3 I D4 I D5 I D6 I D7|
A= l/ips or higher, B-- l/ips or higher
Fig.13 Example of Data Setting Timing in The Serial Mode
The various control settings when in the serial mode are shown in the table below.
Ensure that all control bits are set when the power supply is turned on.
Table 8 Serial Mode Control Settings
SERIAL INPUT CONTROL SIGNALS . .
DATA MODE 1 MODE 2 MODE 3 AT6 to ATO : Attenuation level setting
EMP : De-emphasis ON/OFF switch
D7 0 1 1 MONO, CHS: Stereo/monaural switch
D6 AT6 O 1 RLS : LRCK polarity switch
D5 ATS EMP DBB1 EFS : Dynamic circuit compression
D4 AM MONO DBB2 DOFF ic,hj,C,c,,tricsit,iccyt'1/t,ea, it h
: ynamic curcui SWI c
D3 AT3 CHS D333 D831, D332: Digtal bass boost mode setting
Dit AT2 RLS - DBB3 '. DBB MEGA MAX setting
DI AT1 EFS TCA TCA : Attack time switch
D0 ATO DOFF TCR TCR : Recovery time switch
11 2001-06-19
TOSHIBA TC9438FN
10-2-1 Setting mode 1
Serial setting mode 1 is enabled when D7="L".
(1) Digital attenuator
The digital attenuation command is enabled when D7= L. The attenuation data can be
set in 128 different ways. The relationship with the command's output is shown below.
TabIe-9. Attenuation data/audio data output
ATTENUATION DATA
AT6--ATO AUDIO OUTPUT
7F (H EX) - 0.000dB
7E (HEX) - 0.069dB
01 (HEX) -42.076dB
00 (HEX) - oo
1 (HEX) to 7E (HEX): The attenuation value is obtained with the following equation.
ATT= 208og (input data / 127) dB
Example: When the attenuation data is 7A
ATT = 208og (122/ 127) dB = - 0.349dB
10-2-2 Setting mode 2
Serial setting mode 2 is enabled when D7="H" and D6="L".
(1) Digital de-emphasis filter
Controlled with EMP.
Table 10 Digital De-emphasis Filter Setting
De-emphasis filter
OFF ON
(2) Stereo/monaural output channel settings
Set with MONO and CHS.
Table 11 Stereo, Monaural and Channel Select Settings
L, R-ch output
Stereo output
L-ch monaural output
R-ch monaural output
(*) I "H" or "L"
(3) LRCH (channel clock) polarity switch settings
Set with RLS.
Table 12 LRCK Polarity Switch Settings
RLS L H
Data input R-ch data when LRCK="L" L-ch data when LRCK="L"
2001 -06-1 9
TOSHIBA TC9438FN
(4) Compressor's compression characteristics switch settings
Set with EFS.
Table 13 Compressor Compression Characteristics
(compression ratio) Settings
EFS L H
Compressor's compression
characteristics
Compressor compression
-24di? -36dB
12dB 18dB
Compressor's compression characteristics and compression ratio are shown in Fig. 7.
(5) Dynamic circuit ON/OFF switch settings
Set with DOFF.
Table 14 Dynamic Circuit ON/OFF Switch Settings
DOFF L H
Dynamic circuit ON OFF
The dynamic Circuit's ON/OFF switch settings become invalid when DBB3 is set to "H"
in the following mode 2 settings. The amount of boost when the dynamic circuit is
OFF is shown in tabIe-15.
Table 15 Amount of Boost When The
Dynamic Circuit Is OFF
AMOUNT OF
MID 10.6dB
MAX 15.2dB
10-2-3 Setting Mode 3
Serial setting mode 3 is enabled when D7="H" and D6="H".
(1) Digital bass boost mode settings
Set with DBB1, DBB2 and DBB3.
Table 16 Bass Boost Mode Settings
MODE 1 MODE 2 MODE 3 MODE 4
DBB1 L L H H
DBB2 L H L H
DBB3 LorH LorH LorH LorH
The DBB3 settings are as follows.
DBB3="L" DBB3="H"
MODE 1 : DBB OFF MODE 1': DBB OFF
MODE 2 : DBB MID
MODE 3 : DBB MAX
MODE 4 : DBB MAX+HB
MODE 2': DBB MAX
MODE 3': DBB MEGA MAX
MODE 4': DBB MEGA MAX+HB
2001 -06-1 9
TOSHIBA TC9438FN
(2) Attack time/recovery time switch settings
Set with TCA for attack time and TCR for recovery time.
Table 17 Attack Time Settings
TCA L H
Attack Time 6.3ms 24.3ms
Table 18 Recovery Time Settings
TCA L H
Recovery Time 12.3s 24.6s
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTICS SYMBOL RATING UNIT
VDD - 0.3--6.0
Power Supply Voltage VDA -0.3--6.0 V
VDX - O.3~6.0
Input Voltage Vin -0.3--VDD+0.3 V
Power Dissipation PD 200 mW
Operating Temperature Topr - 35--85 ''C
Storage Temperature Tstg - 55--150 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, VDD = VDX = VDA = 5.0V)
DC Characteristics
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
O eratin Po er s I VDD 4.5 5.0 5.5
p g pp y VDX - Ta = - 35--8YC 4.5 5.0 5.5 v
Voltage (1)
VDA 4.5 5.0 5.5
. VDD Ta = - 25~50°C 2.4 2.7 5.5
3:|¢:;at;n(gm ower Supp y VDX - Operating frequency 2.4 2.7 5.5 V
g l/DA fop, =16.9344MH2 2.4 2.7 5.5
Xl=16.9344MHz
C rr nt C n m ti n IDD1 VDD=VDX=5.0V - 12 20 mA
u e o su p IO I - XI=16.9344MHz 4.5 5.5
DD2 VDD=VDx=2.7V - . .
"H" L I V V .7 - V
Input Voltage " " eve IH - DDXO DD V
L Level VIL 0 - VDDXO.3
Input Current ll' Level IIH - - 10 - 10 pA
L Level IIL
14 2001-06-19
TOSHIBA TC9438FN
AC Characteristics (oversampling ratio-- 192fs)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
THD + N1 1kHz sme wave, full-scale input - - 87 - 80
. . . VDD = VDX = VDA = 5.0V
Noise Distortion 1 1kHz sine wave full-scale in ut dB
THD + N2 ' p - - 82 - 78
VDD =VDX=VDA = 2.7V
S/N V =V =V =5.0V 88 94 -
S/N ratio 1 DD DX DA dB
S/N VDD =VDX=VDA = 2.7V 85 90 -
Dynamic Range DR 1 1kHz s"." wave, -60dB input 85 90 - dB
conversion
Crosstalk CT 1 1kHz sine wave, full-scale input - -90 -80 dB
1kHz sine wave, full-scale
Analog Output Level 1 Aout1 1 inputVDD=VDX=VDA=5.OV - 1250 - mVrms
1kHz sine wave, full-scale
Analog Output Level 2 Aout2 1 inputVDD=VDX=VDA=2.7V - 670 - mVrms
Operating Frequency fopr - VDD=VDX=VDAZ 4.5V 11 16.9344 - MHz
In ut Fre uenc fLR LRCK duty cycle=50% - 44.1 - kHz
p q y fBCK - BCK duty cycle=50% 1.4 2.1168 2.9 MHz
Rise Time tr LRCK BCK . (109f t 90%) - - 15
Fall Time tf - ' pms o o tl - - 15 ns
Delay Time td - BCK I edge -9 LRCK, DATA - - 50 ns
15 2001-06-19
TOSHIBA TC9438FN
It Test circuit 1 : With the use of a sample application circuit
DATA LOUT 20KHz Distortion
S G BCK Application circuit example factor
LRCK ROUT Ideal LPF gauge
1 MCK l
SG : Anritsu : MG-22A or equivalent
LPF : Shibasoku : Built-in 725C distortion factor gauge filter
Distortion : Shibasoku : 725C or equivalent
PARAMETER g02lRJf)1/tEcilfllrs A weight : IEC-A or equivalent
MEASURED A WEIGHT
THD + N, CT OFF
S/N, DR ON
It AC Characteristics Stipulated Point (Input signal stipulation : LRCK, BCK, DATA)
10% 90% 10% 90%
BCK _/_\-
50% tr tf
DATA X X ... X X X
APPLICATION CIRCUIT
The following diagram is for reference purposes only and does not guarantee operations.
-C) MCK GNDD D--t
x-r-t ',GNDX zo', y--oino
t-'Wctc--t XI VDA C) ts 5.0V
16.34M: 220Q
'-=-, C u. v. u. L-ch Analog OUT
30pF I :1 X0 LO D-' + ti, g g
+ g a I 8 2 Fe
5.0V VDX u. GNDA D- N
.ovA 0°
_ -T"r-o-CLATCH(sM) Q VR D-.-s-t
SHIFT(EMP) GNDA I _
XI _,"e-C) .3 , t
EMPH _,",',,.-) ATT (DBB1) RO cy + S 2300 R-ch Analog OUT
u 0 .1
' (DBB2) VDA Ch tr 5.OV 2 2
TC9236AF "ri'--""? - . Jie' }
Single-chip processor Aout "C: DATA ms C)
for CD players
BCK -C) BCK T1 Cy t I -:
CHCK —C LRCK A VDD -l)r 5.0V
16 2001-06-19
TOSHIBA TC9438FN
PACKAGE DIMENSIONS
SSOP24-P-300-0.65A Unit : mm
RflRRRilRRRRRfl d Tr
ii,i)njii 'file/tii-s-c-i-,-.-,-----,-.-,-'',-
0.325TYP " o.22+0.1
=1 ll" o 0.13
8.3MAX "
= 73:02 =
$1 tiii:.', a“?
tht. " e?
I'-.? l l 0.45Hh2
Weight : 0.149 (Typ.)
17 2001-06-19
TOSHIBA TC9438FN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
18 2001-06-19
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