TC9134P ,32-FUNCTION REMOTE CONTROL RECEIVING LSI,ie,Ei'7 ELECTRONIC DE DE-. 5- ic'. " TirrurTTTut 4:5;4k.309724? D017E65 D2ft-77-llTC9134P 32-FUNCT ..
TC9142P ,Quartz PLL Motor ControlQUARTZ PLL MOTOR CONTROLThe TC9142P is a c2-rsos LSI developed for con-trolling the motor of a quar ..
TC9142P. ,Quartz PLL Motor ControlQUARTZ PLL MOTOR CONTROLThe TC9142P is a c2-rsos LSI developed for con-trolling the motor of a quar ..
TC9143P ,for Tape Deck ControlTOSHIBA1 1ri':i'l'ti1'('isttl'"[' DEfFOR TAPE DECK CONTROLTC9143P/T09144P are C-MOS IC for electro- ..
TC9144P ,for Tape Deck Controlfeatures.. Non-Lock type input key ls usable. Mechanicalcontrol in desired made ls possible by plac ..
TC9147BP ,LSI for Static FM/MW/LW 3 Bands Digital Tuning SystemClfl1ljlllj,', 'i"rt;1''ft:"; uh; '; "-rh“ -DTS-8 _ - 6 .,LSI FOR STATIC FM/r-M/Lw 3 BANDSDIGITAL T ..
TDA7073AT ,Dual BTL power driver
TDA7073AT ,Dual BTL power driver
TDA7073AT ,Dual BTL power driver
TDA7073AT ,Dual BTL power driver
TDA7073AT ,Dual BTL power driver
TDA7073AT ,Dual BTL power driver
TC9134P
32-FUNCTION REMOTE CONTROL RECEIVING LSI
mmSHIBA
z '.--:j__7-.‘ T re,
",",ili,'y,i,i,','.i,'i,j,j,is',",i,ii,
rc.sit; tliirit =i-iut"s " v55
ELECTRONIC DE
T091341) 32- FUNCTION POTE CONTROL
RECEIVING LSI
TC9134P is an LSI designed for usd in a
receiver of an Infrared ray remote control
system, and a multifunction remote control
system can be composed in combingtion 'with
TC9132P and LSI for a transmitter.
It ls possible to control 32 functional
Instructions through the remote control and
3 functional ins tructions directly by the key.
. As decorder ls built in and 30 functional
instruction are transmitted In parallel,
external part; are minimized.
. D/A converter ls built in.
. Code detection circuit provided for code
“iDENELI'?
0017365 Cl'
T-77-H
Unit in mm
'Ni-r-Eng-Er-ir-Nr-mr-tek
"aNr.EAEkr%rr%ar.r%rb.auru.uIEaNF%I%rTArEWh..6-gI..
1L2MAX
SSBMAX
1524:025
Lead p1 teh
L4¢Q15
is 254 and tolerance is 1025
against theoretical center of each lead
that is obtained on the basis of No.1 and
No . " leads.
(151'MIN
Juzs-aos
TOSHIBA
6D42A-P
check with the transmitter prevents inter-
PIN CONNECTIONS
ferences from various types of machines
and apparatus. XT 1 42 sq
. LC (or ceramic) oscillation circuit Is " lla "IIs,
G1 I] G AO ll SP
built in. a
_ 02 IV 39 il SP4
I Operating voltage: 4..O N 6.0V. l, E5 SBUSP5'
' “Pa ll 6 57 ll SP6
BPs ll 7 56 il SP7
MAXIMUM RATINGS (Ta = 25''C) m4 [18 sstslltrzt
mg I] 9 "ll s29
CHARACTERISTIC SYMBOL RATING UNIT HPz lilo ssll SPm
HP, tha 52” SP1:
Supply Vo1rage VDD 0 "' 7 pw ON/OFF E12 sin SP1?
Input Voltage VIN -0.3 w vDD+0.3 V 3x2 tiw son sp13
Output Voltage VOUT 0 “Iva v D/AEoult; El: cl 3PM
Power Dissipation PD 600 mW RXIN ”15 27" lie
Egggating Tempera- Topr -30 m 70 "c 022 Iivr 2611 Sp”
Storage Temperature Tstg -55 m 125 “C opt Ills "ll SP“;
tst'ee Us, "ll 3pm
5P2] ll2o 23H 51on
Irmi 21 aall am)
============"""""'"--
nu -"",
,' .g rt) an.“ag-<_~V... n- "',' ie' 3%.. .- 7 'fhh‘. ‘_na ii2,.'itr.hjdhsiet,: - I
TOSHIBA1 ELECTRONIC DE DE ‘11]"178'4? (ti'i'cifi1'if'i'il_ 'i'i' W
TCQT 341?
-T-" nh-l
XT XT VDD GND
l IMING GENERATOR
DETECTION
SHIFT REGISTER
DATA DEC ODER
DATA LATCH
o N/OFF
BPS D/A
HPt CONVERTER
m ____——_—____.__—___ ..
HPS D/A CONTROL
HPti 0P2
EX1 EXz D/A
mAUDID DIGITAL "Dara:
TOSHIBA1
“fcen34p' \\gw
ELECTRI CAL CHARACTERISTI CS
(Unless otherwise specified, VDD " 5.0 ll and Ta
25''C.)
'iiiiiii'iiir.iii 001386? l}
"*7. .._v .V. -_
'T'T'l- H
CHARACTERISTIC SYMBOL TEST CONDITION MIN. MAX. UNIT
Operating Supply Voltage vpo 4.0 6.0 V
Supply Cufrent IDD - 8.0 m
Clmcs "H" Level VIH 3.5 - Il
T Input
EX, Voltage "L" Level VII, - 1.5 ll
u H Level I V =*6.OV - . pA
iii, C; Input woo IH 1 0
H c, Current "L"Eeve1 IIL(C) VIL=0V 1.0 - ph
Ex " u _ I - - .
's"' Input ll Level IH VIH‘e-OV 1 0 PA
BX Current '
P; "L" Level hr, v1L=0v -1000 -.100 HA
, 'lr', Output "ii" Level las - -0.5 mA
3 iiif Current "L" Level I0L o 5 mA
g HPs .
"., CP, Output "H" Level 10H. - -.0.5 mA
* f Current " tt I -
CP3 . L Level 0L 5.0 mA
D/A Error - - - 1 LBS
P Oscillator Frequency fosc - 400 600 kHz
- MTG S H I B A "xr'"'''''
"rqFP..PM"N9q0
TOSHIBA:
ELECTRONIC DE
\V 595,345”
[[5557557 5557555 k, T
PIN DESCRI PTION
'PIN No. ’SYMBOL FUNCTIONAL DESbRIPTION "iTi1?1,ni21(ll1Jl!,,,
1,2 XT, XT Timing oscillator terminal
I 455 kHz ceramic oscillator or L, C oscil- -tiSit
lation circuit is Ieonneceed.
3 W5 Cl,C2,C3 Code designation Input
. If the transmitter code and a code set at
this pin are Identical when compared,1nput tt
ls agcepted. -
6 'ull HP6 'uHPI Continuous signal output
While receiving signal ls being input,,this
output Is kept at "L" level.
In transmission---! l- .
BPI m 6 . 'L----, r---r=
12 " on/off External control input for cyclic output
CPI 'can be controlled not only from the $90.
transmitter but alsolfrom the receiver.
CPI is reversed at "L" level. .
13m15 Ex]. External control Input for D/A converter .
EX2 Operation ls started at "L" ievel when EXl
D/A out is turned up and when EXP. is turned down.
D/A converter output vDD/32 E
VDD ls divided into 32 .
portions and ls output. ”E
16 Rx IN Receiving signal input ' _
An instruction signal with a carrier (h-txr-
signal eliminated is Input.
--.8..".r'...V
"uHt..M..qrs..e" u
AUDID DIGITAL IG: ""
=a--rr-mc _ Tééiéfi? ”f \\
- TOSHIBA1 ELECTRONIC DE
PIN NO. SYMBOL FUNCTIONAL DESCRIPTION I tU1%okJJl1Jlr,
17 CP2 Cyclic signal output
18 CPI When a signal ls received, output is re-
versed. CPI can also be controlled from a
receiving IC.
19 Single-shot signal (single pulse) output
20 SPZZNSPl Wen an Instruction signal is received,
23~42 designated output of "L" level pulse only
1 t d. i
s ransmitte -niaEr--
21,22 VDD,GND Supply voltage applying terminal
OPERATIONAL DESCRIPTION
1. OSCILLATION CIRCUIT
A11 timingé, such as timing with the transmitter, D/A converter clock,
Interval operating clock, are decided by frequencies generated by this
oscillator. 455 kHz ls used as the standard frequency.
The oscillation circuit has the built-in linear amplifier
with a C-NOS inverter, and an oscillator can be easily constructed by
connecting a 455 kRa ceramic oscillator to XT and if pins. In addition,
an oscillation circuit using L, C circuit also can be composed.
Jo1 l C2 . Cl C2
Example using ceramic oscillator Example using L, C circuit]
Ceramic KBR-455B (Kyoto Ceramics)
c1, C2 so I» 150pF
,JTOSHIB "m::=::".::.:':".".:::;u:::::::m‘WWWmmuazxaus-xx". 'tll', Ill,' :::m:.::::::::r:.;zrxmmmmmmmxz.
. “l." ‘31.. “1“." ' vemtqiesuTrdl'_.-au's.r L'1' 2-..
L: ' ' - TOSHIBA}. ELECTRONIC ma Human? anneal] Ll f] "ic
'Sai-a-iii-sc-ia'--'"'".'"-'--'-""''''-'' . - F--'-------, \\ '"",'' T23334P¥
2. RECEIVED SIGNAL INPUT CIRCUIT
A signal received by the light receiving element is amplifierd by
the linear amplifier and input after u carrier signal" has been eliminated.
In this case, care should be taken not to create change in duty and non-
linear waveform due to the demodulation circuit.
to MODULA-
"he)- AuvLrrrsri-Hf-- T2511
L -------------. -u
_3. CHECKING or RECEIVED SIGNAL
Received signal is strictly checked to ascertain if it is a normal
signal or a code is correct.
There are some differences in the methods of checking single pulse and
continuous signal.
3-1) Checking of single-shot signal
Transmission of single-shot signal 'will end after the same signal has
been transmitted in tui, cycles as Illustrated below.
KEY 0N J V L_._
RECEIVED -fmuamrL--frmmmru, F-------
- SIGNAL
F--- IST DATA ---+--- 2ND DATA _
-.*rM.".r.-q-r--.q.r" M...” ""'...-
'.TaTllra'cT,7J,"ir"d;.WdrdTI=r. "" 2...“..2. Cl'"'',','.',,",'?:'',,','.','',',','.''..""':''..'','"' r.. 'CCT/lt/aa'',:",,'.',',",',,' m." .. 'T..",,',' m: . 1:: 2:2: AU DI o D IGITAL [G 'i,'ll,'CT.
_ ' -103 -
I r s L u I
TOSHIBA: -si(:i,li'iiiiihi"'.i'iii,:i'"',ui' 'i'i'iii'cC2)il'ii' e
"'i'iiiui'ici"i"'ii'')i'i; \\
u- '" un-
4...“.
RECEIVED ---D nq
DATA 16-BIT SHIFT REGISTER 17
SHIFT f"" 0.2 0.5 _ _ Q15 Q14 Q1594 C''
CHECKl -Rzacy,
I--------- IST DATA -------f-- 2ND DATA
RECEIVED DATA -f)rTrf0C)C)C)CIrl_r)C)CIDLr-"
BHIFT IJIIJIIIIIIUJIIIJIIJJ
First, the lst data ts stored in the 16-bit shift register by the shift.
sign'al. When the 2nd data is transferred to the shift register by the
shift signal, the lst bit data of the lst data ls forced out to SR17. '
Whenever the lst data and the 2nd data are the normal data, the lst bit .
output Q1 of the shift register and the output from SR17 would be the
same data at all times.
F--- 2ND DATA --------1 .
I lllj_l'
l-IIIJIIH
SHI FT
Accordingly, th of the 16-bit shift register and output Q17 from SR17
are compared by checkl "signal.
.. u.-. _
Since this check signal ls transmitted 16 times, all the data (16 bits)
of the lst and the 2nd data are thoroughly checked.
TOSHIBA TT
TOSHIBA, ELECTRONIC DE _syE:f". myr?iyC7 UDL'NHE 6
"r-il-ll.
With due consideration of frequency margins of the transmitter and
receiver oscillators, the shift signal ls in such a timing as shown
below.
CHEGK1 fl
1'ivi'f'1"u'-r---------stre I‘m} . "
Code Comparison
When the comparison of a11 16-bit data is completed, the code comparison
is executed. At the tine when the comparison of all 16-hit data is com-
pleted, the 2nd data is kept stored in the shift register and the code
data are available at Q13 N Q15.
SHIFT RMISTER
Q13 Q14 Q15 Q16
(,,, . J
Thus, the codes at Cl, C2 and C3 terminals and the outputs from Q13 N
Q14 are compared by Check 2 (16th Check I) signal.
1:; V :21:::::mr;:.:m:::::::r.::::m:x:z:nm::::::;~.:r.:::.:: AU DID D I GITAL I mun:
- 105 -
TOSHIBA1 ELECTRONIC
709134é" \\
Error Signal and End Signal
When error is detected by either the 16-blt data check or code chek,
an error signal ls generated at that point of time and the system ls
reset.
0n the contrary, when everything is ok, an end signal ts generated.
Data receiving is validated by this end signal, and output from the
data decoder begins to operate.
3-2) Checking of continuous signal
Continuous signal is transmitted at intervals of 2-cycle output and
2-cycle pause as Illustrated below.
TRANSMITTED I l
KEY ON
ancmvmn ----7mrtxmy1----reyj.svrr1,-,,,-,
SIGNAL --. --------"
PAUSE PAUSE .
RECEIVED _____
SIGNAL
Continuous signal is checked as in single-shot signal. During the period
of pau.se, the check is also stopped and resumed when data is again
transferred.
3-3) Timing reset
-TOSHIBA
Received signal is checked by a signal generated in the timing citeuit
by' frequency of the oscillation circuit, Shift Checkl and Shift Cheek2,
etc. However, to give' a margin to oscillation frequency, a reset signal
is generated at the tising and falling edges of the received data to
reset the timing circuit, thus constantly synchronizing with the re-
ceived signal.
"F"-tVHbM"._rF0k. am. ummn-u-un mmm- '" '.glr'll','.'dl:
un- "H.-."""--"- .u. mu........4.u mu... ... ."."
' r-106-u-
''''ii''ci'ij'ici'"ti'ils,iiil') ELECTRONIC DE
i.)''''"" i _" \ 'r.-. c'. TCQ'IMFyfi
i' . I _ -re--n"r-/l __
ID-----.-----]
'e _ ar I
_ PRESET 5
" _ .l
- osc . TIMING CIRCUIT i
XT -. _ ,
SHIFT CHECKl CHECKS,
START 2ND _
' LEADER LEADER END
_ cl c2c3 "o" A B c p, E BIT
RECEIVED SIGNAL _II' {M I I I I I 'Cl-f---'
TIMING RESET I I I I
(MIN .)
1mm» mm W
TIMING RESET
(MAX.) II II il II II II III
",tll,'a"/r,"..",'/l', "dll'at:Ta'//l Tr AUDIO DIGITAL "2arar/a
-107- _
_s"_''_'C"'''_''''ri1,'-i'ii",i7iiiiCi':' FCEC+éCNIC.Ué “DE _iltost"1i'iit.iiiCiir'' 0337335 'C.
w' o' "T-. 'TT-il
INSTRUCTION DECODER
If no error is detected in the above checking of recieved signal, '
an end signal ls generated to actuate thé decoder for execution of
instructions. -
SHIFT REGISTER _ TIMING CIRCUIT
Q5 kr tle Q9 ho Q16 -
-.._,-l END l 1 l
CHECK18HIFT CHECKz
c LATCH C . INSTRUCTION DECODER
1 20 21 22 UP/DOWN _2 Pms 6 f
SINGLE-SHOT Yiis'-y.sa-ar-ai-ai--' D/A CONTINUOUS cycmc
CO NTROL SIGNAL
The instruction decoder decodes data bits A N B Into.
o For single-shot signal . 32 instructions
o For continuous signal: 6 instructions
o For D/A control. (up/down) 2 instructions
0 For cyclic signal ' 2 instructions
22.“... WTO S H I B Aevasrr:rcrc", .'.'7K".'1:.‘§""""'L.h“~‘:£1:.m.3:l:.fir££'.5f'"""”'""""" ' T,.''..',,",'.'.".,'.'."..','.""""",,'.','.' "" 'dr.', '",llllt'.,T/d',.'."dMU,''d 1s.vs"xxiavar,:,x: T "Ht.
in " _------
TOSHiéAa
.---. . - YT 15?, 7;. "r' .
ii'iriri'i1"i7i7i"ii"irri''ii
DE 50573u7”0015555 5
T091134?)
"7'U 'n"T-ll
DATA BIT INSTRUCTION DATA BIT. INSTRUCTION DATA BIT INSTRUCTION
A B C D E FUNCTION A B C D E FUNCTION A B C D E FUNCTION
Single-shot Single-shot _
0 0 O 0 0 signal SP 1 1 1 0 1 0 signal SP 12 0 0 1 0 1 D/A up
1 o. O 0 0 " 2 0 0 1 1 O " 13 1 0 1 0 1 D/A down
" n Continuous
0 1 0 0 0 3 1 0 1 l 0 14 0 1 1 0 1 signal HP 1
1 1 O O 0 " 4 0 1 1 1 O " 15 1 1 l 0 1 " 2
0 0 l O 0 " 5 1 1 1 1 0 " 16 0 0 0 1 1 " 3
1 O 1 0 0 " 6 0 0 O 0 l " 17 1 0 0 l 1 " 4
'o 1 1 o o " 7 1 0 o 0 1 "' 18 o 1 o 1 1 " 5
- 1 1 1 0 0 " 8 0 1 0 0 1 " 19 1 1 0 1 1 " 6
" " Cyc 1 l C
0 0 0 1 0 9 1 1 0 O 1 20 0 0 1 1 1 signal CP 1
1 0 1 " 10 1 l 1 " 21 1 0 1 1 1 -" 2
0 1 " 11 1 1 1 1 " 22
5. SINGLE-SHOT SIGNALS SP1 W SP22
S1ng1e-shqt signal Is a single pulse output, falls at the end signal
and rises after approx. 140ms.
KEY ON I ,
swam sHor'c_jtyLr0mrl_r0y1Iim'"1,
END SIGNAL I
BI NGLE-SHOT _
SIGNAL
r---.f"
L--.-,
PAP PROX. "o-i
TC9134P has a built-in 3-circu1t, 5-bit, D/A converter.
D/A CONVERTER CIRCU1T
Wilmmm-‘AUDID DIGITAL "3
am "i"
'"7i7'i7i"iriT?,
ELECT§bNIC~Ué
N: ':.
'tfit)' '_'i'i'i"o''i,"ii"i'iii1'_i,_ "ii'ijtii/'ii'clf"
" -,.v .5;’:j._’..~,
_:.,cLsy., Trc.
- _ - _--"-" ---'--=aua,
"fc.'.-' ’7 'yr-ry'
':rcer,er.."ruSHtBA
----iDowN UP/DOWN COUNTER
CK 5 BITS
Q-1 Q2 Rs Q4 Q5
LADDER NETWORK
n/A OUT
6-2) The clock from the up/down counter is approx. 280 msec when the fre-.
quency generated from the oscillator is 455 kHz,
.-CL..CuCurifi.r-
280 c)
VDD/32(V)
6-3) The up/down control of this D/A converter ls as shown below according
to the above-mentioned instruction decoder output:
O O 1 D 1 UP
6-4) The D/A conirerter 15 capable of controlling up/down directly by the key.
The external input pins EXl and EX2 are the up/down controllers of the
D/A converter.
m.- ----------- n
m...u-......u
'tCi'))')':;"';'),;:'))');';.' ELECTRONIC 'ill;
.www.~§§& “T09134p i
INSTRUCTION DECODER
---tracr
-arc'-1'c.c]
" CL K Ot 531T up/Dowu COUNTER
LADDER NETWORK -----?
The chattering prevention circuit ls provided in the EX input unit to
prevent malfunction due to noise and switch chattering.
EXg mi lllll
--Hr _ Tr'--.-- 10msac
D/A DOWN l
m CLOCK ___J_LFLI_L_FL
D/A. OUT“ . -'T-1----1-----n--n.L,,
-~-AUDID DIGITAL "Ta
lStig “41-94143 E
_-»»- “
_-._ _ P=Wa.aWtlM=." A
TOSHIBA, ELECTR NIc DE DEB Hua?au
_'' T69134P , "ii1iii1iiii1iiiiii
POWER o N
VDD I 1
PRES ET II
é iifiFirG U n
71 "i-r-n
-7. CYCLIC SIGNALS (CPI, CP2)
Cyclic signal ls a signal by which output is inverted when It is
received. Data from the instruction decoder is inverted by the T-type
flip-flop. '
PW ou/oFF
-------- _ f
", a a
INSTRUCTION tf, h - 'Pt tIPI
DECOL‘ER a J, é J,
Further, CPI can be Inverted through the external input key Pil ON/OFF,
and is used for the power ON/OFF.
m l nnu-u _ III Imu-r-m-umu- nnnnnn luwlu lllll m "E"".--" _ n l uuww
:.zvafrt3SH I BArrarars ,. -uH-.req"motr.rt..rrrHttar"s.rrtr..qtttt W " """ " .
'm-ate-Ce" _,Aq,r'.
TOSHIBA, ELECTRONIC DE
T?iy17 I301/?T30 3 n_-“h:
T091 MI?
T- "l"l-ll
8. CONTINUOUS SIGNAL
Continuous signal Is kept at "L" level during the period when it is
-being transmitted from the transmitter.
DATA -Z,
$333,? "----rsArA --c-H--- PAUSE ---f---DArA ---F-- PAUSE __H I
Similar to the single-shot signal, output timing of the eontinuous signal
ls such that it is inverted to "L" level when an end signal is generated
after the checking of 16 bits of the 2nd data of the lat data has been
completed, and it becomes error when the first Checkl signal for the
E second data of next data is generated after the transmission has stopped,
and then, it is Inverted to "H" level.
IN TRANSMISSION L
5 DATA r---) L-.l L ------------ m___-
cHEcKl r- Illlllillllllllt -lllll
ERROR SIGNAL '- I
HP b F
:"aAUDID DIGITAL "Tara:
';i"iii7iri'r.t', ELECTRONIC nap Batman? I';'';;';''';;''; 'lt?1iii''iiif-2l' C...,
'"“"‘T‘c9134ré """""" \\ "r-nn-h
INITIALIZATION AT TIMER OF POWER 0N
Wen power is turned on, it Is necessary to initialize the system for
Initialization of the Internal state and presetting of the D/A converter.
This initialization can be executed by simultaneously setting 'terminals
of 12 Pin, 13 Pin and 14 Pin at time of the power 0N.
That is, the initialization is executed when capacitors are connected to 12
Pin, 13 Pin and 14 Pin.
ou/omr
t c RUP
Rup=3 5 la] (TYP)
_ T c=looopv
INITIALIZATION
POWER ""Y l f
ON , .
- r------------------!
12 PIN Tr * For the duration of Initialization,
------/
0 . 5 msec or above Is required after
ID PIN
- rising of the supply voltage (VDD) .
' " PI N
------c-------,
INITIALIZATION
OUTPUT *
--/ DURATION OF INITIALIZATION
:rw- c,,,,,,,,',, s A I B A:m':r....';-:_:r::..":m-z'm-xxm:“::..mnxmmxzzmmrawhz::2::::r:.:n::r::r::..::‘:. Jra'/gl'at.'C'd:.Tl'dL",Ta"a'h''d', ::mun. 31.:2‘...J.37.3.2l'"Ti":“m.1:':.':i'::u:::'
- 1 l4 -
- - "7i"i7rii''r.77rii"i''7iCiiiii:-i:' na 'itli'i, Hua72u?nm?fine 7 Div“;
. .1 7=77+//"n___
EXAMPLE IF APPLIED CIRCUIT AT RECEIVING UNIT
. 7 _ 10v
TP8601 -----O Exam
MKII? 2801816x3 (GR , ' '
_ . com a tl Toko E.k.
Ci ". ?'31--a:3tsor,q:ats
Ci) - L: 4 _ 6: 100T
" CG fo=38kHz:-39
cc O c =ssoopF
Con trol Signal
‘HJ waw a
SP1234
P 'r E 9 I 5 l P _
- Rx VDD
XT xr Cy ca Rs HPg ti 4 5 2 KEELEY £74115!!sz m CPlchSPzgSle
M tht) ty I L
u it} ffl? I _
Receiving I I . j/e
Amplifier
Detection
8 9 10111213 " 1516 1'7 181981720
V _ J L J
Control Signal T Control Signal
3" I, '/srac'rravr, :m AUDIO DIGITAL "2:v/arc
www.ic-phoenix.com
.
