TC90A11F ,Multi System 3 DIM / DNR ICTC9OA11FT(‘QnA11FMULTI SYSTEM 3DIM. DNR IC (FOR VCR)TC90A11F is the digital video signal processor, ..
TC90A11F ,Multi System 3 DIM / DNR ICTC9OA11FT(‘QnA11FMULTI SYSTEM 3DIM. DNR IC (FOR VCR)TC90A11F is the digital video signal processor, ..
TC90A13F ,3 LINE DIGITAL Y/C SEPARATION ICTC9OA13N/FT(‘QnA1 2N T(‘QnA1 "‘UVIIIUII' I‘UVIIIUIThe TC90A13N and TC90A13F separate luminance (Y) ..
TC90A13F ,3 LINE DIGITAL Y/C SEPARATION ICTC9OA13N/FT(‘QnA1 2N T(‘QnA1 "‘UVIIIUII' I‘UVIIIUIThe TC90A13N and TC90A13F separate luminance (Y) ..
TC90A13N ,3 LINE DIGITAL Y/C SEPARATION ICTC9OA13N/FT(‘QnA1 2N T(‘QnA1 "‘UVIIIUII' I‘UVIIIUIThe TC90A13N and TC90A13F separate luminance (Y) ..
TC90A17F ,PAP / PIP / POP Controller for NTCS / PAL Wide RVTC9OA17FT(‘QnA17FThe TC90A17F is a PAP (picture and picture)/P|P/POPcontrol IC with built in ADC an ..
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TDA6651TT/C3 ,TDA6650TT; TDA6651TT; 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
TDA6651TT/C3 ,TDA6650TT; TDA6651TT; 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
TDA6651TTC3 ,TDA6650TT; TDA6651TT; 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
TDA6651TTC3 ,TDA6650TT; TDA6651TT; 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
TC90A11F
Multi System 3 DIM / DNR IC
TOSHIBA TC90A11F
TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC90A1l ll F
MULTI SYSTEM 3DIM. DNR IC (FOR VCR)
TC90A11F is the digital video signal processor, which
reduces the noise on the playback video signal of VCR,
with the external video memory IC (2Mbit FIFO type).
This IC is available for NTSC, PAL, etc. in world wide area. _----------"',
FEATURES
o Built-in 2 channels A/D converters.
(for Luma & for Chroma)
o Built-in 2 channels D/A converters. A channel can be
selected the output signal, Luma (Y) or Y/C mix. The
other is for chroma output signal.
QFP100-P-1420-0.65A
Weight : 1.1g (Typ.)
. Multi system, NTSC (3.58MH2, 4.43MH2), PAL and NTSC on PAL. (applying YNR only at SECAM)
o Built-in the clock generaters.
at NTSC : x4 PLL of fsc (chroma subcarrier frequency)
at PAL : VCXO circuit locked the color burst.
o Built-in the digital H-PLL circuit and the digital V-PLL circuit.
0 3 kinds of NR system, Frame comb (NTSC only), Field comb, Line comb (for Trick mode).
0 Applicable 2Mbit memory IC : PPD42280 (NEC), MSM518221
o Built-in the digital CTI (color detail enhancer)
0 " control
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert or other rights of the third
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-04-21 1/22
TOSHIBA TC90A11F
BLOCK DIAGRAM
DOC PV/PH/BLNK
Y Input
YNR r Detail Y/C (Y) Output
Enhancer
C Input I
" C Out ut
CNR r MOD P
(DOC) _
C-Sync
Input SYSTEM
CLOCK fsc Input
n,-- l
CLOCK DATA 'r' T
2Mbit memory IC
1998-04-21 2/22
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TOSHIBA
TC90A1 1 F
PIN DESCRIPTION
No. NAME I/O FUNCTION REMARKS
1 ch Output Writing clock to memory IC High |eve|>2.4V, low |eve|<0.6V
2 RSTW Output Write reset pulse to memory High |eve|>2.4V, low |eve|<0.6V
3 VDD1 - Digital voltage supply (5V) -
4 POTO Output
5 POT1 Output
6 POT2 Output
7 POT3 Output . Out ut hi h |eve|>2.4V,
8 POT4 Output Output of test monitor CCI", logv |eve|<0.6V
9 POTS Output
10 POT6 Output
11 POT7 Output
12 GND1 - Digital GND -
13 PWM Output VCXO control output High |eve|>2.4V, low |eve|<0.6V
14 RETO Input Reset pin of internal logic -
15 ADTO Input
16 ADT1 Input
17 ADT2 Input
18 ADT3 Input Pulse input for testing Threshold of high |eve|<2.4V
19 ADT4 Input Threshold of low level>0.8V
20 ADT5 Input
21 ADT6 Input
22 ADT7 Input
23 GND2 - Digital GND -
24 FS Input Clock input (for VCXO) Injcelrnal lc BIAS,
mlnlmum input level<1up-p
25 VDD2 - Digital GND -
26 vcxo Output Buffer output of vcxo $2233: $335213“
27 VDD3 - Voltage supply of VCXO -
28 INVO Output Inverter output of VCXO -
29 INVi Input Inverter input of VCXO -
30 GND3 - GND of VCXO -
31 VDD4 - Voltage supply of x4 PLL Recommend digital voltage supply (5V)
32 GND4 - GND of x4 PLL Recommend digital GND
33 PLL FIL - Loop filter of x4 PLL -
34 FSC Input Fsc input for x4 PLL Injce-rnal D.C BIAS,
mlmmum input level<:1Vp-p
35 GND5 - GND of AD converter Recommend analog GND
36 VDD5 - Voltage supply of AD conv. Recommend analog voltage supply (5V)
37 CLAMP Output CLAMP BIAS for Y input 3/10xVDD (5V)
38 GND6 - GND of AD converter Recommend analog GND
39 YrefH - High level REF. for Y-ADC -
40 YIN Input Y (Luma) input Typ. input :;1:\/3F)7_p' signal CLAMP by
1998-04-21 4/22
TOSHIBA
TC90A1 1 F
EL? NAME I/O FUNCTION REMARKS
41 YrefL - Low level REF. for Y-ADC -
42 BIAS1 - BIAS of AD converter Common to Y-ADC and C-ADC
43 VDD6 - Voltage supply of AD conv. Recommend analog voltage supply (5V)
44 CrefL - Low level REF. for C-ADC -
45 CIN Input c (Chroma) input i'ytrinnajuBtlAs , 121%101
46 CrefH - High level REF. for C-ADC -
47 GND7 - GND of AD converter Recommend analog GND
48 BIASZ - BIAS of DA converter -
49 Cbias - BIAS of C-DAC -
50 Vref - Reference voltage of DAC -
51 COUT Output C (Chroma) output 3:;OFF (fix to VDD) controlled by BUS
52 VDD7 - Voltage supply of DA conv. Recommend analog voltage supply (5V)
53 Ybias - BIAS of Y-DAC -
54 GND8 - GND of DA converter Recommend analog GND
55 You, Output Y(Luma)orY/Coutput f)1/e,ryiiSgPe),itrolledl,yBus
56 GND9 - Digital GND -
57 VDD8 - Digital voltage supply (5V) -
58 BLNK Input Chroma mute (ON/OFF by BUS) l/ill:,),",':?,':),')'--''""'' ON
59 PVPH Input Chroma mute (ON/OFF by BUS) 2g: éYL/Czpi'gigar' =mute ON
60 MODO Input
61 MOD1 Input Test mode select -
62 MOD2 Input
63 GND10 - Digital GND -
64 PSTO Input
65 PST1 Input
66 PST2 Input
67 PST3 Input Test signal input Threshold of high |eve|<2.4V
68 PST4 Input Threshold of low level >0.8V
69 PST5 Input
70 PST6 Input
71 PST7 Input
72 DOC Input DOC pulse input <0.8V-9DOC ON, >2.41/-9OFF
73 CSYNC Input C-SYNC input VTH : <2.4V/ >0.8V, hysteresis : 0.4V
74 KILL Input Color killer >2.4V-9killer ON, <:0.8V-9OFF
75 IZCCK Input Click input of IZC BUS VTH : <2.4V/ >0.8V, hysteresis : 0.4V
76 IZCDT Input Data input of IZC BUS -
77 ACK Output Acknowledge output Pc BUS High |eve|>2.4V, low |eve|<0.6V
78 VDD9 - Digital voltage supply (5V) -
79 SWCONT Output BUS decode output High |eve|>2.4V, low |eve|<0.6V
80 RSTR Output Read reset pulse to memory High |eve|>2.4V, low |eve|<0.6V
1998-04-21 5/22
TOSHIBA TC90A11F
El"? NAME I/O FUNCTION REMARKS
81 Rck Output Reading clockto memory IC High |eve|>2.4V, low |eve|<0.6V
82 MI7 Input
83 MI6 In t .
PU Data input from memory IC Threshold of high |eve|<2.4V
84 MI5 Input Threshold of low level>0.8V
85 MI4 Input
86 M07 Output
87 M06 Output Output high level>2 4V
Data out ut to memor IC . '
88 M05 Output p y Output low |eve|<0.6V
89 M04 Output
90 VDD1O - Digital voltage supply (5V) -
91 4fsc Output System clock monitor High |eve|>2.4V, low |eve|<0.6V
92 GND11 - Digital GND -
93 M03 Output
94 M02 Output Output high level>2 4V
Data out ut to memor IC . '
95 MOI Output p y Output low |eve|<0.6V
96 M00 Output
97 MB Input
98 MI2 In t .
PU Data input from memory IC Threshold of high |eve|<2.4V
99 MII Input Threshold of low level>0.8V
100 MIO Input
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD - 0.3-- + 6.0 V
Input Voltage VIN -0.3--VDD +0.3 V
Power Dissipation PD(Note) 1.75 W
Operating Temperature Topr -10--75 "C
Storage Temperature Tstg -40--125 "C
(Note) Ta = 25°C
1998-04-21 6/22
TOSHIBA TC90A11F
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Ta = -10-75''C, VDD =4.75~5.25V)
CHARACTERISTIC PIN SYMBOL COIJl-Igf'EON MIN. TYP. MAX. UNIT
Supply Current - IDD - - - 165 mA
(*A) IhHI - 2.4 - -
. (*B) VIHZ - 2.4 - -
1:5:lshold of High (*C) VIH3 - 4.0 - - V
59 (PV/PH) 1hH4 - 1/2VDD + 0.3 - -
58 (BLNK) l/IHS - 1/6VDD + 0.2 - -
(*A) V|L1 - - - 0.8
(*B) Wu - - - 0.8
Threshold of Low Level (*C) lhL3 - - - 1.0 V
59 (PV/PH) lhL4 - - - 1/2VDD - 0.3
58 (BLNK) l/ILS - - - 1/6VDD -0.2
Input Current (High) (*A), (*B), (*C) In.” - - 10 - + 10 pzA
Input Current (Low) (*A), (*B), (*C) 'IHZ - - 10 - + 10 PA
Output High Level - VOH tlu,,, 2.4 - - V
Output Low Level - VOL loL=4mA - - 0.6 V
Hysteresis Level - VHS - - 0.4 - V
(*A) 15-22, 64, 72, 74, 82, 85, 97, 100
(*B) 73, 75
(*C) 14, 60-62
1998-04-21 7/22
TOSHIBA TC90A11F
AC CHARACTERISTICS (Ta =25°C, VDD=5V)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input Level (Y) Yin White 100% at pin 40 - 1.6 2.0 Vp-p
Input Level (C) Cin 100 IRE Chroma at pin 45 - 1.15 2.0 Vp-p
Fsc (Pin 34) Input Level Lsc Sine wave at pin 34 0.3 1.0 2.0 Vp-p
Operation Frequency Fsc 1.0Vp-p sme wave at 3.47 3.58/4.43 4.58 MHz
Range pm 34
FS (Pin 24) Input Level Lfs - 1.0 - - V
I R f AD
:0an: ange o AD IN Pin 40, pin 45 3/10 VDD - 7/10 VDD v
Output Signal Level at Yin =1.6Vp.p
Pin 55 You, Vref= 2.5V (pin 50) - 2.0 - Vp-p
Output Chroma Level Cout Cin =1.15Vp_p- - 1.43 - Vp-p
at Pin 55 & Pin 51 Vref=2.5V (pin 50)
Output Impedance Zo - 200 350 700 n
Set Up Period to Read
the Data of Memory TMIS - 25 - - ns
Hold Period to Read T - 3 - - ns
the Data of Memory MIH
TWRH 20 - -
Clock Pulse Width to TWRL . 20 - -
Memory IC TWWH Load impedance 15pF 20 - -
TWWL 20 - -
TRSTRS 15 - -
TRSTRH 10 - -
Pulse Timing to TRSTWS 15 - - ns
Memory IC TRSTWH 10 - -
TMOS 15 - -
TMOH 10 - -
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TOSHIBA TC90A11F
PC-BUS OUTLINE
The IZC-BUS has two wires, serial data (SDA) and serial clock (SCL) which carry information between
the IC's are connected to the bus line. The bus is considered to be busy after the "Start Condition".
The bus is considered to be free again after the "Stop Condition".
A HIGH to LOW transition of the SDA line while SCL is HIGH, defines a Start Condition.
A LOW to HIGH transition of the SDA line while SCL is HIGH, defines a Stop Condition.
Every bytes put on the SDA line must be 8bit long. Each byte has to be followed by acknowledge
bit. Each SDA and SCL has to be pulled up the voltage supply via a resistor.
DON'T ............ Don't vary the data while clock is high level at data transmission.
Don't vary the data while clock is high level
Start Condition Stop Condition
This IC adopts the sub address format. Send the sub address and the data alternately after the slave
address. If the first bit of the sub address which is sent first is changed to "I", some data can be
sent continually. (Refer to follow)
INPUT SUB ADD. AND DATA ALTERNATELY
i"'""'"," Slave Address Sub Address Data of "A" Sub Address Data of "B" ..._...
: : "A" "B"
Data 0 0H0 * * * . * 0H0
i _ f '
". ..... alternately - alternately
INPUT DATA CONTINUALLY AFTER SUB ADD.
1llEf1l1ff
CLOCK '_..-....)''.'..':-;... l'lllllllllfllllrllllf.lf
v"""'"'"." Slave Address Sub Address Data of "N" Data of "N+1" Data of "N+2"
: .' "N"
0 Fr--
i _.... continually
CLOCK _'......"":....... 1llllNllrNf
Start Condition
lf HHLHH
Stop Eeh'ciition
1998-04-21 10/22
ZZ/H LZ'170‘8GBL
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(1531) 0 (1531) 0 (QUON) 0 (1531) 0 (1531) SS
(1531) 0 (BUON) 0 (BUON) 0 (BUON) 0
(BUON)0 (1531)0 (1531)o (1531)o (1531)v5
(1531) o (1531) o (BUON) o (1531) o
(1531) 0 (1531) 0 (1531) 0 (1531) 0 (1531) 6S
(9U0N) o (aUON) o (1531) o (1531) o
(1531) 0 (1531) 0 (1531) 0 (1531) 0 (1S31)8§
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(GUON) 0
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(BUON) 0 101 ‘19P A 10 9d°|S
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VEIHSOJ.
TOSHIBA TC90A11F
DETAIL EXPLANATION OF BUS CONTROL
1. Motion detector function and the setting of BUS bit
It Motion detectors decide the picture (part) is near the moving or the still by detecting the
differential level between the input signal and the delayed signal (a frame or a field).
0 The NR circuit receives the result of motion detectors and makes the "K factor" reduce to "0"
(NR OFF) at the parts of the moving picture.
0 The middle range of "K factor" have 5 steps from the setting value to "o", and the offset value,
which is the starting point to reduce the "K factor", and slope is programmable by IZC BUS
control.
0 YNR is controlled by the Y-motion detector only, and CNR is controlled by both the Y-motion
detector and the C-motion detector. But in case of that the color level is small and the motion
of Y-signal is small, CNR is controlled by only the Y-motion detector to decrease the cross color
component.
K factor
L ____________ T--
(NR effect)
Offset
Still picture-Result of Motion detector "h/loving picture
1998-04-21 12/22
TOSHIBA TC90A11F
Color level
Deep 'i..' ,
CNR controlled by both the Y-Motion
Det. and the C-Motion Det.
Reference level - ............................................................. i' ......................................................... . .
CNR controlled by the Y-Motion
Det. only
Moving level of
Y-signal
Still picture Reference level Moving picture
It BUS control data
co K factor of YNR (Sub address 40H ; D7~D4)
K factor can be changed by 14 steps from 0 to maximum. K factor of YNR increases in
proportion to the setting data of these bits.
© Limiting level of YNR (Sub address 40H ; Dr-Do)
The limiting level can be changed by 16 steps from 0 to maximum. Limiting level of YNR
increases in proportion to the setting data of these bits.
(3) K factor of CNR (Sub address 41H , D7~D4)
K factor can be changed by 14 steps from 0 to maximum. K factor of CNR increases in
proportion to the setting data of these bits.
© Limiting level of CNR (Sub address 41H ; Dr-Do)
The limiting level can be changed by 16 steps from 0 to maximum. Limiting level of CNR
increases in proportion to the setting data of these bits.
(h) Offset of Y motion detector for YNR (Sub address 42H ; D7~D4)
This data can be changed by 16 steps from 0 to maximum. When the data is smaller, the
motion detector make the K factor of YNR reduce more near the still picture, so, YNR effect
is smaller. Conversely when the data is bigger, K factor doesn't decrease more near the
moving picture, so, the afterimage comes into view on the moving picture.
1998-04-21 13/22
TOSHIBA TC90A11F
Slope of Y motion detector for YNR (Sub address 42H ; D3, D2)
This data can be changed by 3 steps.
"00" =steep slope, "01" =middle, "10" =gentle slope
Offset of Y motion detector for CNR (Sub address 43H ; Dr-Da)
This data can be changed by 16 steps from O to maximum. When the data is smaller, the
motion detector make the K factor of CNR reduce more near the still picture, so, CNR effect
is smaller. Conversely when the data is bigger, K factor doesn't decrease more near the
moving picture, so, the color blur increases on the moving picture.
Slope of Y motion detector for CNR (Sub address 43H ; D3, D2)
This data can be changed by 3 steps.
"00" =steep slope, "01" =middle, "IO" =gentle slope
Offset of C motion detector for CNR (Sub address 44H ; Dr-Da)
This data can be changed by 16 steps from 0 to maximum. When the data is smaller, the
motion detector make the K factor of CNR reduce more near the still picture, so, CNR effect
is smaller. Conversely when the data is bigger, K factor doesn't decrease more near the
moving picture, so, the afterimage comes into view on the moving picture.
Slope of C motion detector for CNR (Sub address 44H ; D3, D2)
This data can be changed by 3 steps.
"00" =steep slope, "01" =middle, "10" =gentle slope
Reference level of Y motion detector for cross color (Sub address 45H ; Dr-04)
This data can be changed by 16 steps. When the data is bigger, the countermeasure effect of
the cross color works more near the moving picture.
Reference level of Y motion detector for cross color (Sub address 45H ; Dr-Do)
This data can be changed by 16 steps. When the data is bigger, the countermeasure effect of
the cross color works to the bigger color signal level.
ON/OFF of Y motion detector for YNR (Sub address 46H ; D7)
Y motion detector for YNR is forced OFF at "I". (YNR is always ON.)
ON/OFF of Y motion detector for CNR (Sub address 46H ; D6)
Y motion detector for CNR is forced OFF at "1".
(CNR is controlled by only C motion detector.)
ON/OFF of C motion detector for CNR (Sub address 46H ; D5)
C motion detector for CNR is forced OFF at "1".
(CNR is controlled by only Y motion detector.)
Wide mode of the moving picture part (Sub address 46H ; D4)
The moving picture parts widen for :2 cycle of clock at "I".
1998-04-21 14/22
TOSHIBA TC90A11F
© The moving picture parts to black (Sub address 46H ; D3) ............ (Test mode)
The moving picture parts is replaced to black by the result of motion detector at "I".
Y motion detector result (Sub Address 4FH ; D5)="I"
C motion detector result (Sub Address 4FH ; D5) ="1"
This function is only for the evaluation. Don't use this function for the other aim,
ll) YNR and CNR OFF (Sub address 46H ; D2)
The result of all motion detectors is replaced to the moving picture at "1".
(YNR and CNR is always OFF.)
1998-04-21 15/22
TOSHIBA TC90A11F
2. The setting of BUS for the television standards
f/l DATA c??glslm "0" "1 " NTSC 443 NTSC PAL SECAM (SN¥§CS)
46 D0 443NTSC 358NTSC 443NTSC o 1 o 1 o
47 D0 De-mod OFF NORMAL OFF 0 o o 1 0
4A D7 PAL NTSC PAL 0 o 1 o o
4F D1 BPF OFF NORMAL THROUGH o o o 1 o
50 D3 sw CLK in FS Fsc 1 1 o 1 1
50 D2 VCXO OFF ACT STOP 1 1 o 1 1
50 D1 PLL OFF ACT STOP 0 o 1 o o
51 D7 50/60 60Hz 50Hz o 0 1 1 o
51 De 4.43/3.58 3.58MH2 4.43MHz o 1 1 1 o
53 D3 C-DAC ON OFF ON 0 o o o 1
54 D1 Mod OFF NORMAL OFF 0 o o 1 o
54 D0 Y/C mix OFF Y-ONLY YC-MIX 1 1 1 1 o
55 D2 PAL/ NTSC PAL NTSC - 1 o - -
C) 443NTSC (Sub address 46H , Do)
VCO frequency of the 4fsc PLL is changed by this bit.
0 : fsc=3.58MHz, 1 : fsc=4.43MHz
© De-modulation OFF (Sub address 47H ; Do)
The chroma demodulator is ON/OFF by this bit. Select OFF at only SECAM mode.
0 : ON, 1 : OFF
(3) PAL (Sub address 4AH ; D7)
The chroma modulating and de-modulating system is selected by this bit.
0 : NTSC, 1 : PAL
(4) BPF OFF (Sub address 4FH ; D1)
The chroma BPF is ON/OFF by this bit. Select OFF at only SECAM mode.
0 : ON, 1 : OFF
© Switch of the clock input (Sub address 50H ; D3)
The clock input terminal is selected by this bit.
0 : pin 24 (for VCXO), 1 : OFF : pin 34 (for 4fsc PLL)
(B) VCXO OFF (Sub address 50H ; D2)
The VCXO driver of the burst PLL is ON/OFF by this bit.
0 : ON, 1 : OFF
Ct) PLL OFF (Sub address 50H ; D1)
The 4fsc PLL is ON/OFF by this bit.
0 : ON, 1 : OFF
1998-04-21 16/22
TOSHIBA TC90A11F
50Hz/6OHz (Sub address 51H ; D7)
This bit is for selection of the field frequency.
0 : 60Hz, 1 : 50Hz
© 4.43MHz/3.58MHZ (Sub address 51H , D6)
This bit is for selection of the system clock frequency by fsc.
O : fsc=3.58MHz, 1 : fsc=4.43MHz
ll) C-DAC ON (Sub address 53H , D3)
Chroma output (at Pin 51) is ON/OFF by this bit.
0 : OFF, 1 : ON
© Modulation OFF (Sub address 54H , D1)
The chroma modulator is ON/OFF by this bit. Select OFF at only SECAM mode.
0 : ON, 1 : OFF
© Y/C mix OFF (Sub address 54H ; Do)
This bit is for selection of the output signal at Pin 55, composite video (Y/C) or Luma only (Y).
O : Y/C mix, 1 : Y only
(gl) PAL/NTSC (Sub address 55H ; D2)
This bit is for selection of the detection system of burst PLL, NTSC or PAL. When you will only
use the burst PLL at NTSC signal, set this bit "I".
0 : PAL, 1 : NTSC
o, SW control (Sub address 4DH ; D6)
This bit is for the external SW control. Pin 79 (SWCONT) is the decoding terminal of this bit.
0 : Low, 1 : High
(Note) When the bit of "Y-DAC ON" (Sub add 53H ; d4) is "I'', the Y-DAC output terminal
(Pin 55) is fixed "Hi" (near the VDD level).
1998-04-21 17/22
TOSHIBA TC90A11F
3. The adjustment of the internal logic timing by BUS data
C) Delay of chroma mute for BLNK pulse (Sub address 48H ; Dr-Ds)
The color component of the output signal at Pin 51 (Cout) or/and Pin 55 (Yout) is OFF during Pin
74 (BLNK) is low. This color mute timing can be shifted by the data of these bits.
© Timing adjustment of the delayed signal from the memory IC (Sub address 49H ; Dr-Do)
These bits are for the timing adjustment between the input signal and the delayed signal from
the external memory IC. Normally, these bits are set as follows for each NR mode.
Field or Frame NR mode ............. 17H =(**010111)
Line NR mode ....................... 08H =(**001000)
(3) Timing adjustment of the video signal and the C-sync (Sub address 49H ; Dr-Do)
To save the bits data for the memory IC, the NR effect is OFF except the picture parts of the
video signal. This timing is made from the C-sync (Pin 73), and the horizontal position can be
sifted by these bus bits data.
So, set the data for these bits to meet the timing between the action period of WCK (Pin 1) and
the picture parts of internal video signal, that is Ips later than the signal of Yin (Pin 40).
(4) V mask position for burst PLL (Sub address 51H ; D4--D2)
The detector of the burst PLL stops during the Vertical Blanking period. This period can be
selected by bus data. But, normally select the longest period (D4=0, D3=1).
Front of V mask period : "D4=0" ; early, "D4=1" ; late
End of V mask period : "(D3, D2)=(0, 0)" ; early
"(D3, D2)=(0, l)" ; center
"(D3, D2)=(1, x)" ; late
(h) Burst gate position for VCXO (Sub address 52H ; Dr-DI)
The gate pulse of burst PLL is made from C-sync, so you have to adjust the timing of this pulse
to the internal burst position, that is 500ns later than the signal of Cin (Pin 45). This gate pulse
can be observed at Pin 13 (PWM) under the test mode as follows.
Test mode for the observation of the burst gate pulse
Sub Address 4BH ; D1=0
Sub Address 4EH , D6--1
Sub Address 4EH , D3=1
Sub Address 55H ; D1=1
C6) Delay of Y signal (Sub address 54H ; D7, D6) (Note) Fix 0 at "Y/C Delay"=1 (C delay mode)
Delay of C signal (Sub address 54H ; D5, D4) (Note) Fix 0 at "Y/C Delay" =0 (Y delay mode)
These bits are for the adjustment of Y/C timing at output. First, select the Y delay or C delay by
the bit of "Y, C Delay" (Sub Address 48H ; D1).
1998-04-21 18/22
TOSHIBA TC90A11F
4. The others
C) Color mute control
The terminal who make the chroma output OFF is as follows.
It BLNK (Pin 58) ; Mute the color where is the characters at OSD super impose mode.
0 PVPH (Pin 59) ; Mute the color where is vertical blanking period, because the color is not
0 KILL (Pin 74) ; Make the color OFF when the input signal is the B/W signal.
The functions of BLNK (Pin 58) and PVPH (Pin 59) can be made OFF by bus control as follows.
It C-Mute OFF (Sub Address 48H ; D2)=1-9BLNK (Pin 58) is ignored.
It PV/PH OFF (Sub Address 53H ; D2)=1-aPVPH (Pin 59) is ignored.
2) Memory IC (Sub address 4CH ; D1)
0 : PPD42280 (by NEC), 1 : MSM518221 (by OKI)
(3) Field/frame (Sub address 4CH , Do)
0 : Frame NR (NTSC only), 1 : Field NR
(il) Standard/non standard (Sub address 50H , D5, D4)
The video signal from the PC and the TV game etc. is different from the television standard. This
IC detects the input signal is the standard or not, and usually makes the NR effect OFF
automatically. But the manual select is available by bus control.
D5 ; 0 : Automatic, 1 : BUS control (D4)
D4 ; 0 : Standard, 1 : Non-standard
(Note) On the trick mode of VCR, the input signal may be regarded as the non-standard
because the number of lines in a field is different from on normal play back. If you
need the (line) NR effect on the trick mode, you select the standard fix mode by bus.
(h) Line NR (Sub address 51H ; D5)
The line NR mode is usually used on the trick mode of VCR, because the field correlation is small
in this case. This IC doesn't have the internal line memory, so the external memory is used on
the line NR mode, too.
0 : Frame/Field NR, 1 : Line NR
© Drop-out compensation
This IC have the function that replace the input signal by the delayed signal during low level at
Pin 72 (DOC). But this function can not be used at the field/frame NR mode, because the
delayed signal is noting at the sync parts. So you can use this function at the line NR mode only.
It Y-DOC (Sub Address 4FH ; D7)=1 .... Y signal component is replace by DOC pulse at Pin 72.
o C-DOC (Sub Address 4FH ; D6)=1 .... C signal component is replace by DOC pulse at Pin 72.
1998-04-21 19/22
TOSHIBA TC90A11F
Ct Chroma noise cancel
It C-N.C. ON (Sub Address 53H , D7)
0 : OFF, 1 : ON
It Limiter level of C-N.C. (Sub Address 53H ; D6, D5)
00:2,10:4,01:8,11:16
Y detail enhanced level (Sub address 56H ; D7, D6)
00 : 0 (OFF), 01 :0.25, 10 : 0.5, 11 : 1.0
S) C detail enhancer (Sub address 56H ; D5, D3, D2, D1)
This function is the enhancement of chroma signal level near the edge of Y signal.
It D5 ; Edge detecting level ........ 0 : Low, 1 : High
It D3, D2 ; Enhancement level of the chroma detail
00 : 0.5, 01:1.0,10:1a11:2.0
It D1 ; C detail enhancer OFF
0 : ON, 1 : OFF
DESIGNING FILTER CIRCUIT
a) Input low-pass filter
This Iow-pass filter is used to limit the frequency bandwidth of the input signal to below a half of
the clock frequency. If the input signal contains a high frequency component and this input filter is
not, it may interfere with clock frequency inside the IC, generating a frequency component that can
be removed by an output filter. (Reflected distortion)
b) Output low-pass filter
This filter is used to remove clock frequency components (including harmonics) in the IC's output
signal, as well as remove the reflected distortion at input.
CAUTION
This device is electrostatic sensitive device, so care must be taken in handling and storage to prevent
deterioration or damage by means of shorting electrically all pins with use of aluminum foil or
conductive mat.
Even in assembled on board, it is necessary to protect against surge or inductive noise from input,
output and power supply line.
1998-04-21 20/22
TOSHIBA
TC90A1 1 F
APPLICATION CIRCUIT
Digital f f f f f f f To memory IC
5V f C C f C C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
-(2 80
Ci') 79 SW control
'Q, 78
G 76 O Pc DATA
GD 75 0 Pc CLK
(i) 74 O C-killer
(iii 73 o C-SYNC
C9: 72 0 DOC pulse
Cii 71 '
Ci 70 1
Ci 69 '
sv-Ei) 68 1
Ci' 67 1
" w-tiii 66 1
TC9 0 A 1 1 F
o-f?, 65 t
(i? 64 ,
(Lo) o- o-(18] 63 '
"-(iii 62
"-tiii 61
Cj'-,--,!,.),) 58 PV/PH/BLNK
f -=- 24 57
- GE 56
-o-Ci 55 Youtput
's??., 54
28 53 -M-4
29 52 -o-4
ll 30 51 Coutput
, L 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 , 0 Analog 5V
l 1111 1 ll: {WWW
ff TTIT f fff OAnalogGND
O Y input
- O fsc input
1998-04-21 21/22
TOSHIBA TC90A11F
OUTLINE DRAWING
QFP100-P-1420-0.65A
23.81‘03
20.0i0.2
0.825TYP
14.0i02
0.575TYP
03:0.1
GAE T ___
0.8i0 2
Weight : 1.1g (Typ.)
Unit : m
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