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TC9083F ,1 CHIP PIP CONTROLLER FOR MULTI COLOR SYSTEMTC9083N/FT(‘QDRRN T(‘QDRRFwvvvvli' I‘vvvvlThe TC9083N and the TC9083F provide ADC, DAC andmemory. T ..
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TC9083F
1 CHIP PIP CONTROLLER FOR MULTI COLOR SYSTEM
TOSHIBA
TC9083N/F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9083N, TC9083F
1 CHIP PIP CONTROLLER FOR MULTI COLOR SYSTEM
The TC9083N and the TC9083F provide ADC, DAC and
memory. This is a PIP controller IC correspond to MULTI
COLOR system. TC9083N and TC9083F can realize PIP
processing with only two ICs by combining TC9083N or
TC9083F to TA87958F (PAL/NTSC/SECAM V/C/D IC) or
TA8779F (NTSC V/C/D IC).
FEATURES
Including 129Kbit DRAM, 6bit ADCX1, 6bit DACx3,
clamp circuit, Multiplexer and controller.
Corresponding to Multi Color System.
Sub-picture size are 1/9 and 1/16 (1 /16 mode is
available in case that horizontal line number of sub-
picture is equal to horizontal line number of main
picture.)
Frame color is selectable with Fixed 4 colors (black, red,
green and cyan), other programmable 64 colors and no
frame.
Frame width can be controlled.
Display position is 4 corners. Display position trimming
can be controlled independently on each corner.
Including vertical compensation filter.
Still picture mode in sub-picture.
Fixed color display for no program channel.
" Bus interface.
5V single power supply.
SDIP42 or QFP80 package.
TC9083N
SDIP42-P-600-1.78
TC9083F
QFP80-P-1420-0.80A
Weight
SDIP42-P-600-1.78 : 4.13g (Typ.)
QFP80-P-1420-0.80A : 1.6g (Typ.)
2001 -06-1 9
TOSHIBA
DIAGRAM
TC9083N/F
T C 9 0 8 3 N / F
L C f - M A DE-MPX fl -
R-Y p -c A - p - D - VERTICAL - RAM_ - EDGE COLOR C - R-Y
F M x c FILTER 129Kblt SELECTER x RGB
B-Y B-Y
-c p - 3 _.:>_. MATRIX
TA8779F/ - GATED TIMING TIMING R G B
OSC - GENERATOR GENERATOR - Y
TA8795BF - (SUB) (SUB) (MAIN) "=,, FROM
J; J; 1 RGB B-Y MAIN
V/C/D , t , INTERFACE Clsiu/c/r)
VDCN (SUB) J“ SYSTEM Cr-''-
HDCN (SUB) f CONTROL
REGISTER le-
COMPOSITE VIDEO f f _G.
CRT DRIVER
SWITCHING SIGNAL 1/ t t -
AV SWITCH - FROM p-CON HDPN
SDA SCL VDPN(MAIN)
twogo m1 (MAIN)
VIDEO IN 2 l C Bus
VIDEO IN 3
2 2001 -06-1 9
2001 -06-1 9
SCL 6 57; YO
NC 6 a NC
SDA (u: $ DABIAS CLMPT 6 3 Y5
NC G <3 NC VDCN 6 Es) V55
V99 («:3 g VREFL HDCN («3 5 BO
NC m g NC V55 G 3 R0
CKCI \. @ VDD SCL (u: g YO
NC (.3 ‘3 NC SDA (.3 :1 DAB IAS
CKCO@ g4 VREFH V99 6 g VREFL
NC C3: 3 NC CKCI @ :33 VDD
TESTO (f: E CLMP CKCO @
NC (g: 3, NC TESTO Ca:
TEST1 Q; g; ADBIAS TEST1 (3:
RESETN (g: 2 Bl RESETN @
NC (3: 3 NC VDPN (5/
VDPN @ :3 RI HDPN (3:
NC @ 5-; NC TESIOO @ g) V55
HDPN 6;; 4:, YI TESIO‘I (g; g) vDD
NC (3: 5, NC TESIOZ (3: g DCPO
TESIOO @ @ V55 TESIOB C75: 5 DCPI
NC (:3 5; NC TESIO4 (3: ® VDD
TES|O1 (,5: :5) VDD TESIOS (g: u CKPO
NC @ ,5 NC V55 (:3 g CKPI
TESIOZ (g 1: DCPO
TC9083N
TC9083F
D, CKPO
(ii) NC
D CKPI
ED l/SS
29 TESIOS
ii) NC
D TESIO4
CE) TESIO3
TOSHIBA
TERMINAL CONNECTION DIAGRAM (TOP VIEW)
TC9083N/F
TOSHIBA
TC9083N/F
TERMINAL FUNCTION
TC9083N (SDIP42 PIN)
El"? PIN NAME I/O FUNCTION CONDITION
1 CLMPT I Input for Clamp Timing Normally : 5.0Vp-p
2 VDCN I Vertical Sync. For Sub-picture Sync. negative, Normally : 5.0Vp-p
3 HDCN I Horizontal Sync. For Sub-picture Sync. negative, Normally : 5-0Vp-p
4 l/SS Digital GND For Including RAM
5 SCL I " Bus Clock Input
6 SDA I/O " Bus Data Input
7 VDD Digital VDD For Including RAM Normally : 5.0V
8 CKCI I Gated-OSC For Sub-picture
9 CKCO O Gated-OSC For Sub-picture
10 TESTO I Test Terminal Normally : connect with Digital VDD
11 TEST1 I Test Terminal Normally : connect with Digital VDD
12 RESETN I System Reset Normally : connect with Digital VDD
13 VDPN I Vertical Sync. For Main-picture Sync. negative, Normally: . 5.0Vp-p
14 HDPN I Horizontal Sync. For Main-picture Sync. negative, Normally: 5.0Vp-p
15 TESIOO I/O Test Terminal Normally: . connect with Digital GND
16 TESIO1 l/O Test Terminal Normally : connect with Digital GND
17 TESIOZ I/O Test Terminal Normally : connect with Digital GND
18 TESIO3 I/O Test Terminal Normally : connect with Digital GND
19 TESIO4 I/O Test Terminal Normally : connect with Digital GND
20 TESIO5 I/O Test Terminal Normally : connect with Digital GND
21 l/SS Digital GND For Internal Logic
22 CKPI I Gated-OSC For Main-picture
23 CKPO O Gated-OSC For Main-picture
24 VDD Digital VDD For Internal Logic Normally : 5.0V
25 DCPI I External Delay Input For Clamp
26 DCPO C) External Delay Output For Clamp
27 VDD Digital VDD For Including RAM-Plate Normally : 5.0V
28 I/SS Analog GND For ADC
29 Yl I Analog Luminance Signal Input Normally : l-OI/p-p
30 RI I Analog R-Y Signal Input Normally : 1.0Vp-p
31 BI I Analog B-Y Signal Input Normally : 1.0Vp-p
32 ADBIAS I Bias For Including ADC
33 CLMP I Clamp Control
34 VREFH I Reference Voltage For A/D Normally : 5.0V
35 VDD Analog VDD For ADC, DAC Normally : 5.0V
36 VREFL I Reference Voltage For DAC Normally : 3.0V
37 DABIAS I Bias For Including DAC
2001 -06-1 9
TOSHIBA
TC9083N/F
Kl"?- PIN NAME I/O FUNCTION CONDITION
38 YO 0 Analog Y Signal Output Normally : 2.0Vp.p
39 RO o Analog R-Y Signal Output Normally : 2.0Vp-p
40 BO 0 Analog B-Y Signal Output Normally : 2.0Vp-p
41 l/SS Analog GND For DAC
42 YS 0 Main, Sub-picture Switching Timing Sync. positive, Normally : 5.0Vp-p
TC9083F (QFP80 PIN)
2f. PIN NAME I/O FUNCTION CONDITION
1 SCL I IZC Bus Clock Input
2 NC -
3 SDA I/O IZC Bus Data Input
4 NC -
5 VDD Digital VDD For Including RAM Normally : 5.0V
6 NC -
7 CKCI I Gated OSC For Sub-picture
8 NC -
9 CKCO O Gated OSC For Sub-picture
10 NC -
11 TESTO I Test Terminal Normally : connect with Digital VDD
12 NC -
13 TEST1 I Test Terminal Normally : connect with Digital VDD
14 RESETN I System Reset Normally : connect with Digital VDD
15 NC -
16 VDPN I Vertical Sync. For Main-picture Sync. negative Normally : 5.0Vp-p
17 NC -
18 HDPN I Horizontal Sync. For Main-picture Sync. negative Normally : 5.0Vp_p
19 NC -
20 TESIOO l/O Test Terminal Normally : connect with Digital GND
21 NC -
22 TESIO1 I/O Test Terminal Normally : connect with Digital GND
23 NC -
24 TESIO2 l/O Test Terminal Normally : connect with Digital GND
25 TESIO3 I/O Test Terminal Normally : connect with Digital GND
26 NC -
27 TESIO4 I/O Test Terminal Normally : connect with Digital GND
28 NC -
5 2001-06-19
TOSHIBA TC9083N/F
tel. PIN NAME I/O FUNCTION CONDITION
29 TESIOS I/O Test Terminal Normally : connect with Digital GND
30 NC -
31 l/SS Digital GND For Internal Logic
32 NC -
33 NC -
34 CKPI I Gated OSC For Main-picture
35 NC -
36 CKPO O Gated OSC For Main-picture
37 NC -
38 VDD Digital VDD For Internal Logic Normally : 5.0V
39 NC -
40 DCPI I External Delay Input For Clamp
41 DCPO 0 External Delay Output For Clamp
42 NC -
43 VDD Digital VDD For Including RAM-Plate Normally : 5.0V
44 NC -
45 l/SS Analog GND For ADC
46 NC -
47 YI I Analog Luminance Signal Input Normally : 1.0Vp-p
48 NC -
49 RI I Analog R-Y Signal Input Normally : 1.0Vp-p
50 NC -
51 BI I Analog B-Y Signal Input Normally : 1-0Vp-p
52 ADBIAS I Bias For including ADC
53 NC -
54 CLMP I Clamp control
55 NC -
56 VREFH I Reference Voltage For A/D Normally : 5.0V
57 NC -
58 VDD Analog VDD For ADC, DAC Normally : 5.0V
59 NC -
60 VREFL I Reference Voltage For DAC Normally : 3.0V
61 NC -
62 DABIAS I Bias For including DAC
63 NC -
2001 -06-1 9
TOSHIBA TC9083N/F
tll'. PIN NAME I/O FUNCTION CONDITION
64 YO 0 Analog Y Signal Output Normally : 2.01/p-p
65 RO 0 Analog R-Y Signal Output Normally : 2.01/p-p
66 NC -
67 BO 0 Analog B-Y Signal Output Normally : 2.0Vp-p
68 NC -
69 VSS Analog GND For DAC
70 NC -
71 YS 0 Main, Sub-picture Switching Timing Sync. positive Normally : 5.0Vp-p
72 NC -
73 NC -
74 CLMPT I Input for Clamp timing
75 NC -
76 VDCN I Vertical Sync. For Sub-picture Normally : S.OVp-p
77 NC -
78 HDCN I Horizontal Sync. For Sub-picture Normally : 5.0Vp-p
79 NC -
80 VSS Digital GND For Including RAM
7 2001-06-19
TOSHIBA TC9083N/F
FUNCTION SUMMARY
1. Clamp timing
The clamp pulse showed in
is generated by inputting composite sync. (negative)
or horizontal sync. (negative) to CLMPT terminal (ref. ).
The CLMPT terminal can input clamp pulse from external circuit directly.
In this case, CLMPS of IZC bus register (sub-address 10H 3rd data, select clamp circuit) set 1, DCPI
terminal is pulled down to GND level and DCPO terminal is open.
Y, R-Y and B-Y signal, which are outputted from sub-picture demodulator IC, are clamped to
match dynamic range of ADC. Clamp level of each signal are
Y : 0V
R-Y : 0.5V
B-Y : 0.5V
CLAMPS=1
_..-"-- Clamp pulse
RC time constant CLAMPS = 0
V/C/D Yout - picture data
Clamp pulse
1.5/15
8 2001-06-19
TOSHIBA TC9083N/F
2. Multiplex circuit
After clamp circuit, Y, R-Y and B-Y are multiplexed to change to time division video signal.
(Y)-a(R- Y)-a(Y)-9(B-Y)-a(Y)-9(R- Y)-a(Y)-a(B-Y)
Multiplex is effected above order.
3. AD converter
Il/p-p analog multiplexed video signal is converted to 6bit digital multiplexed video signal.
Sampling frequency are
when 1/9 size ____________ 6.0MH2
when 1/16 size __________ 4.5MHz
4. Vertical compensation filter
Vertical compensation filter improves vertical resolution with compensating each line data by
using 2Kbit SRAM when horizontal line data is thinned out to match sub-picture size 1/9, 1/16.
Difference vertical line number is compensated with changing coefficient of filter in 525/625
(horizontal line) Multi display mode.
SUB-PICTURE SIZE 'YSTEM/tfeet/l)""") TAP NUMBER COEFFICIENT
525/525 3 1/4 1/2 1/4
1/9 625/625 3 1/4 1/2 1/4
525/625 4 1/8 3/8 3/8 1/8
625/525 3 1/4 1/2 1/4
1/16 525/525 4 1/8 3/8 3/8 1/8
625/625 4 1/8 3/8 3/8 1/8
Provided that In 525/625 mode, 2lines are took in with 1/8, 3/8, 3/8, 1/8, 3/8, 3/8, 1/8.
In 625/625 mode, 2lines are took in with 1/4, 1/2, 1/4, 1/2, 1/4.
5. Memory
129Kbit DRAM is used as sub-picture 1 field memory.
9 2001-06-19
TOSHIBA TC9083N/F
6. Sub-picture take in area
Sub-picture size 1/9 Sub-picture size 1/16
Horizontal Y = 168dot Horizontal Y = 128dot
R-Y = 42dot R-Y = 32dot
B-Y = 42dot B-Y = 32dot
Vertical (Sub-picture size 1/9) (Sub-picture size 1/9, 1/16 common)
Main/Sub 525line/625Iine=268H 525line/525Iine =228H
625line/525Iine=210H 625line/625Iine =252H
. Explanation about take in timing
7.1. Horizontal take in area (Sub-picture size 1/9)
I“ -------------- 635/15 ------------- -A
HDCN I I I
Horizontal take in area I ------- 672xCKC -
Clock conversion address 1 I I
CKC(12MHZ) 0 48 720
7.2. Horizontal take in area (Sub-picture size 1/16)
HDCN l I
Horizontal take in area
------- 682xCKC-------
Clock conversion address I
CKC (1 2MHz) 0
Horizontal take in area can be trimmed as follows ; (Clock conversion)
At 1/9picture, -24, -12, +12 from preset
At 1/10picture, -32, -16, +16 from preset
7.3. Vertical take in area (Sub-picture size 1/9, 1/16 common)
7.3.1. Main =525|ine, Sub=525line
Vertical take in area
--_-_-- 228H--------
Clock conversion address I I I
HDCN 0 27 255
7.3.2. Main=525line, Sub=625line (Sub-picture size 1/9)
Vertical take in area
----- 266H--------
Clock conversion address I l
HDCN 0 27 293
10 2001-06-19
TOSHIBA
7.3.3. Main =625line, Sub=625line (Sub-picture size 1/9, 1/16 common)
Vertical take in area
---- 252H--------
Clock conversion address I l
HDCN 0
7.3.4. Main =625line, Sub=525line (Sub-picture size 1/9)
Vertical take in area
--------- 210H~-------
Clock conversion address
TC9083N/F
TOSHIBA TC9083N/F
8. Sub-picture display area
Sub-picture size 1/9 Sub-picture size 1/16
Horizontal Y =160dot Horizontal Y =120dot
R-Y = 40dot R-Y = 30dot
B-Y = 40dot B-Y = 30dot
Vertical 525line = 74H Vertical 525line = 56H
625line = 84H 625line = 60H
9. Explanation about display timing
9.1. Main =525|ine, Sub=525|ine or 625line, Size=1l9
9.1.1. Horizontal sub-picture display area
HDPN l-l, |_l
I 336xCKP
Horizontal sub-picture I r ----- 1 -
display area I ( ,' 18.7,us
l : l l l
Clock conversion address I I l l I
CKP(18MHz) 0 128 Left 464 640 Right 976
display display
9.1.2. Vertical sub-picture display area
Vertical sub-picture
display area I I I
I l I , I
I I I I I
Clock conversion address I : I l I
HDPN 0 32 Top 106 160 Bottom 234
display display
9.2. Main =525|ine, Sub=525|ine, Size=1/16
9.2.1. Horizontal sub-picture display area
HDPN |_l I_I
I 256xCKP
--------- 1
Horizontal sub-picture l ' l -
display area I ( ,' I 142/25 I
I I I I I
Clock conversion address I I I l _ I
CKP(18MHz) 0 160 Left 416 672 Right 928
display display
9.2.2. Vertical sub-picture display area
VDPN L_I cl-
Vertical sub-picture
display area
F _________ 1
IZ-sts-ri-cl
40 Top 96 168 Bottom 224
display
Clock conversion address
display
All of above data are preset value.
Display area can be trimmed as follows.
To horizontal direction, -28--127step (1step is CKPx4)
To vertical direction, -64-63step (1step is 2H)
12 2001-06-19
TOSHIBA TC9083N/F
9.3. Main=625|ine, Sub=525line or 625line, Size=1/9
9.3.1. Horizontal sub-picture display area
HDPN I I I I
I 336xCKP
Horizontal sub-picture l I ------- I -
display area I I I 18.7/15
I l I I I
Clock conversion address 1 I I I I
CKP(18MHz) 0 128 Left 464 640 Right 976
display display
9.3.2. Vertical sub-picture display area
Vertical sub-picture
display area
F--isii--Z]
4 160 Bottom 242
display
Clock conversion address
32 Top 1
display
9.4. Main=625|ine, Sub=625line, Size=1/16
9.4.1. Horizontal sub-picture display area
HDPN I I I I
256 x CKP
Vertical sub-picture
display area
Clock conversion address
HDPN 0( Left ) 4 6 672( Right) 928
display display
9.4.2. Vertical sub-picture display area
Horizontal sub-picture
display area
r _________ 1
F-tso-rr-cl
Clock conversion address I I
CKP(18MHz) 40 ( Top ) 1 o 168 (Bottom) 228
display display
All of above data are preset value.
Display area can be trimmed as follows.
To horizontal direction, -28--127step (Istep is CKPx4)
To vertical direction, -64--63step (Istep is 2H)
13 2001-06-19
TOSHIBA TC9083N/F
10. ODD/EVEN field detection timing.
TC9083N and TC9083F detect ODD/EVEN field at each main and sub-picture internally. So, the
phase of HDCN and VDCN, or, HDPN and VDPN, which are inputted from external, must be
controlled. CTHM and PTHM are field detection pulse. These are made by HDCN and CKC
(12MHz), or, HDPN and CKP(18MH2). If the trailing of VDCN and VDPN, which are inputted from
external, exist during detection pulse is high, ODD field is detected. And if that trailing exist
during detection pulse is low, EVEN field is detected.
The leading of VDCD and VDPN must exist in center of detection pulse so that ODD/EVEN field
detection is stable.
The period of VDCN and VDPN must be more than 1H.
10.1. Write mode (Sub-picture) ODD/EVEN field detection
HDCN I I
CTHM I
ODD field
EVEN field
VDCN I
Pulse width must be more than 1H
10.2. Read mode (Main-picture) ODD/EVEN field detection
10.2.1. HDPN is "H" <1024XCKP
PTHM -I
ODD field
EVEN field -l
Pulse width must be more than 1H
10.2.2. HDPN is "H" >1024XCKP
HDPN I I i
PTHM I l
ODD field
EVEN field I
Pulse width must be more than 1H.
14 2001-06-19
TOSHIBA TC9083N/F
(Note) Limitation about HDCN (Sub-picture Horizontal sync. signal) width (Low period)
1. X is Low period of HDCN.
2. Y is a period start from leading edge of HDPN, and end at start point of sub-picture display.
X must be smaller than Ci).
© : XSY-25(Clock cycle) (Clock : sub-picture)
HDCN - X -
F---- y -
HDPN I
Sub-picture Display p ----- Display Area =1
_--sub-picture Display Starting
11. Frame color setting
Frame color can be selected 4 color (black, red, green and cyan) as fixed color via " BUS.
Besides this, frame color can be selected 64 colors with changing upper 2bit in the 6bit for Y, R-
Y, B-Y, which structure frame color, via " BUS. Set frame color with BACKC=0, black color
change to selected color to CDATA 5-0 via pc Bus.
12. Frame width control
Frame width can be controlled with changing the pulse width of main/sub switching pulse.
Control range is follows;
Horizontal 0--8dot 4dot step
Vertical 0--2line/field Iline step
13. Display position control
Preset position is Lower right. Besides this, display position can be set to upper right, upper left
and lower left via " Bus. Display position can be trimmed with Horizontal 8bit and Vertical 7bit.
Control range is follows;
Horizontal - 128 ~ + 127 steps 4dot /step
Vertical -64-- +63 steps Iline/ step
14. Still picture mode
Still picture can be displayed with stopping writing to field memory for reading same picture
15. Fixed color display for no program channel
Sub-picture is fixed color via 12C Bus.
Display color can be selected 64 colors with changing upper 2bit in the 6bit for Y, R-Y, B-Y,
which structure display color, via " Bus. Set display color with BACK-- l, black color change to
selected color to CDATA 5--o via " Bus.
15 2001-06-19
TOSHIBA
16. Multi color mode
TC9083N/F
Main-Picture
525Line 625Line
Sub- 525Line C) O
Picture 625Line C) C)
At 525line/625Iine or 625line/525Iine mode, 1 field is displayed for avoiding V dancing.
17. DA converter
This DA Converter converts 6bit sub-picture digital data to 21/p-p analog signal. Bandwidth is
18. Pc Bus
IZC Bus control is provided.
Slave address 2E(H), 2F(H)
Sub-address
00 (H), 10(H), 20 (H), 30 (H)
Sub-picture position trimming data (sub-address 20 (H)) should be sent after 20ms in NTSC mode,
or 24ms in PAL mode, sending sub-picture position data (sub-address 10(H)).
APPLICATION CIRCUIT
1. GATED OSC
SUB CLOCK
TRF1171D
CKCO '-6)
u, 3 4
CKCI o"-'f- '-OD
12MHz (DENKENSANGYO)
2. CLAMP 3. CLAMP CONTROL
CLMP DCPO o-,
rr":':." T DCPI o-l
TIME CONSTANT J
1.5/15
MAIN CLOCK
TRF1 164D
Mgr 3.. H?
18MHz (DENKENSANGYO)
4. A/D BIAS
AD BIAS
5. D/A BIAS
DA BIAS
16 2001-06-19
TOSHIBA TC9083N/F
12C BUS CONTROLLED FORMAT SUMMARY
Bus controlled fomat of TC9083N and TC9083F are based on " Bus Control format of Philips.
Data Transfer Format
I S I Slave address I 0 I A I Sub address I A I Data 1st I A I Data 2nd I A I Data 3rd I A I P I
I 7bit I 8bit I 8bit I 8bit I 8bit
MSB MSB MSB MSB MSB
S : Start Condition
P : Stop Condition
A : Acknowledge
(1) Start and Stop Condition (2) Bit Transfer
r--1 r"1 l l l l
SDA Ai, /- -1 i/i' SDA /s EX! A
i E a i a a a a
.-..-. I I I I
SCL I s j) I S I I P I SCL y (l II (l
Start Condition Stop Condition / I I I
SDA cannot change. I
SDA can change.
(3) Acknowledge (4) Slave Address
from MasterM 1e7High"mpedance A6 A5 A4 A3 A2 A1 A0 R/W
SDA I I -
from Slave High |mp_ed:nce N I
from Master 5 N /1 l I 8 N I 9 N
SCL |____:
Purchase of TOSHIBA IZC components conveys a license under the Philips PC Patent Rights
to use these components in an " system, provided that the system conforms to the "
Standard Specification as defined by Philips.
17 2001-06-19
TOSHIBA
TC9083N/F
IZC Bus Register
TC9083F and TC9083N have write address of 00101110 (2EH).
Sub-address 00H (No program data)
Sub-address 10H
1st DATA (Preset : COH)
MSB LSB
POSI POSO COLOR1 COLORO STILL 0 0 ON / OFF
2nd DATA (Preset : 02H)
MSB LSB
SPAL MPAL BACK 0 0 0 1 0
3rd DATA (Preset .' 60H)
MSB LSB
YCDEL1 YCDELO WR1 WRO 0 0 0 CLAMPS
POSI, 0 : Sub-picture display position 4corners (Preset 11 Right bottom corner)
00 -9 Left top corner, Ol-o Right top corner, 10 -9 Left bottom corner
11 -eRight bottom corner
COLOR1,0 : Frame color (Preset 00 Green)
00 -etiireen, 01-9Cyan, 10 -eRed, 11 -yVariable (*)
(*) Color setting : Sub-address 20H CDATA5--0, Preset 000000 : Black
STILL : Still mode (Preset 0 : Moving picture)
O-O/loving picture, I-9Still picture
ON/OFF : Sub-picture display ON/OFF (Preset 0 Undisplay)
0 -9 Undisplay, 1 -9 Display
SPAL : Sub-picture change 525line/625line (Preset 0 525line)
0-e525line, I-y625line
MPAL : Main-picture change 525line/625line (Preset 0 525line)
0-e525line, I-y625line
BACK : No program channel processing (Preset 0 No processing)
0 -9no processing,
1-yNo program channel processing (*)
(*) Color setting .' Sub-address 20H CDATA5~0, Preset 000000 :Black
YCDL1, 0 : Sub-picture's luminance Y phase control
(Preset 01 .' Luminance Y color difference R-Y/B-Y same phase)
00 -aY phase is 1dot fast to R-Y/B-Y
01-yLuminance Y color difference R-Y/B-Y same phase
10 -ay phase is 1dot delay to R-Y/B-Y
11 -ey phase is 2dot delay to R-Y/B-Y
18 2001-06-19
TOSHIBA TC9083N/F
WR1, 0 : Write position (horizontal) (Preset 10 : Write from active area)
00 -e4dot fast to default
01-y2dot fast to default
10 -yWrite from active area
11 -a2dot delay to default
CLAMP : Clamp circuit (Preset 0 : Internal Circuit)
0-ylnternal Circuit, 1 -aExternal Circuit
(Note) "o" should be put into open bit in above register
Sub-address 20H
1st DATA (Preset : 00H)
MSB LSB
H7 H6 H5 H4 H3 H2 H1 H0
2nd DATA (Preset : 00H)
MSB LSB
V6 V5 V4 V3 V2 V1 V0 BACKC
3rd DATA (Preset : 00H)
MSB LSB
C DATA 5 C DATA4 C DATA 3 CDATA2 C DATA1 C DATA0 0 0
H7-0 : Horizontal display adjustment (Preset 00000000)
8bit Ts compliment data (4dot/1LSB)
Left Right
V6-0 : Vertical display adjustment (Preset 0000000)
7bit 2's compliment data (2Line/1LSB)
Bottom Top
BLACKC : Setting the resister for variable color data (Preset 0 : Frame color selection)
0 -yFrame color setting
I-yDisplay color setting for no program channel is resister
CDATA5-0 .' Variable color (Preset 000000)
CDATAS, 4-rMSB, 2ndMSB (Y signal)
CDATA3, 2 -eMSB, 2ndMSB (R l signal)
CDATA1, 0-YMSB, 2ndMSB (B-Y signal)
(Note) "o" should be put into open bit in above register
19 2001-06-19
TOSHIBA
TC9083N/F
Sub-address 30H
1st DATA (Preset : 57H)
MSB LSB
9/ 16 YSHW6 YSHWS YSHW4 YSHW3 YSHW2 YSHW1 YSHWO
2nd DATA (Preset : 98H)
MSB LSB
YSVW5 YSVW4 YSVW3 YSVW2 YSVW1 YSVWO YSDEL1 YSDELO
3rd DATA (Preset : B2H)
MSB LSB
YSC6 YSC5 YSC4 YSC3 YSC2 YSC1 YSCO 0
9/16 : Sub-picture size select (Preset 0 1/9)
0 -9 1 l9, 1 -9 1 / 16
YSHW6-0 : YS horizontal width (Preset 1010111)
Straight binarydata
No frame -91010110
4dot width frame -9 1010111
8dot width frame -9 1011000
YSVW5-0 : YS vertical width (Preset 100110)
Straight binarydata
No frame -9 100100
1Line width frame -9100101
2Line width frame -9100110
YSDL1, 0 : YS horizontal delay (Preset 00 No delay)
00 -plNlo delay 01-a0.5dot delay
10-91.0dot delay 01-a1.5dot delay
YSC6-0 : YS center (Preset 1011001)
Straight binarydata
1LSB -o2dot move
Recommendation
: 1011101
(Note) "o" should be put into open bit in above register
2001 -06-1 9
TOSHIBA TC9083N/F
MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage I/SS, VDD Vss--vsss 6.0 V
Input Voltage VIN -0.3+VSS--VDD+0.3 V
Power Dissipation PD 800 mW
Storage Temperature Tstg - 55--125 °C
RECOMMENDED OPERATING CONDITION
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Power Supply Voltage VDD 4.5 5.0 5.5 V
Input Voltage VIN 0 VDD V
Operating Temperature Top, -20 70 ''C
21 2001-06-19
TOSHIBA TC9083N/F
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Condition : VDD=4.5~5.5V, Ta = -20--70oc, VSS=0V
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Current Consumption IDD - - - 140 mA
High Level CMOS V - *1 4.0 - - V
Input Voltage SMTC IH *2 4.0 - -
Low Level CMOS V - *1 - - 1.0 V
Input Voltage SMTC IL *2 - - 1.0
I C L"H" Level IIH1 - V|N=VDD *3 -10 - 10 A
nput urrem"L" Level IIL1 - 1hN=Vss *3 -10 - IO /2
IOH = - 1mA *4 'fri, - -
"H"L I V - .
Output eve OH I - -4mA *5 VDD v
Voltage OH - - 1.0 - -
" " IOL=1mA *6 - - 1.0
L Level VOL - loL=4mA *5 - - 1.0
SMT Hysteresis Voltage VH - *2 - 0.6 - V
*1 CKCI, TESTO, 1, RESETN, CKPI, DCPI
*2 CLMPT, VDCN, HDCN, SCL, SDA, VDPN, HDPN (SDA is inputted)
*3 CKCI, TESTO, l, RESETN, CKPI, DCPI, CSN, VDCN, HDCN, SCL, SDA, VDPN, HDPN, TESIOO~5
(SDA is inputted)
*4 SDA, TESIO0--5 (SDA is outputted) CLMPT
*5 CKCO, CKPO, DCPO, YS
*6 TESIO0--5, SDA (SDA is outputted)
AC CHARACTERISTICS
Condition : VDD=5.OV, Ta = -20--70oc, VSS=0V
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operational Frequency CKP - *1 - 18.0 - MHz
Condition CKC - *1 - 12.0 -
O t t L din T ilin Tim tr2 - CL=30.0pF *2 - - 10.0 n
u pu ea I g ralll g I e tf2 - CL=30.0pF *2 - - 10.0 s
*1 CKPI, CKPO
*2 CKPO, CKCO, DCPO, YS
22 2001-06-19
TOSHIBA
ADC Characteristics
Condition : VDD = 5.0V, Ta = - 20~70°C, VSS = 0V
TC9083N/F
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Non-Linear Error
VDD = SV, VREFH = 5V
f CKCl=12MHz
(ADCK=6MHz)
-2.5 - 2.5 LSB
Differencial Non-Iinear Error
VDD = SV, VREFH = 5V
f CKCl=12MHz
(ADCK=6MHz)
-3.0 - 3.0 LSB
Full SCA
Analog Input
VDD = SV, VREFH = 5V
f CKCl=12MHz
(ADCK=6MHz)
0.88 - 1.06
Voltage
Zero SCA
VDD = SV, VREFH = 5V
f CKCl=12MHz
(ADCK=6MHz)
0 - 0.06
DAC Characteristics
Condition : VDD = 5.0V, Ta = - 20--7ty'C, VSS = 0V
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Non-Linear Error
VDD = SV, VREFL = 3V
f CKPl=18MHz
(DACK=9MHz)
- 1.0 - 1.0 LSB
Differential Non-Iinear Error
VDD = 5V, VREFL = 3V
f CKPl=18MHz
(DACK=9MHz)
-1.0 - 1.0 LSB
Full SCA
Analog Input
VDD = SV, VREFL = 3V
f CKPl=18MHz
(DACK=9MHz)
4.8 - 5.0
Voltage
Zero SCA
VDD = SV, VREFL = 3V
f CKPI=18MHz
(DACK=9MHz)
3.0 - 3.2
Error Between Channel
VDD = 5V, VREFL = 3V
f CKPl=18MHz
(DACK=9MHZ)
-0.2 - 0.2 V
Output Dynamic Range
VDD = 5V, VREFL = 3V
f CKPl=18MHz
(DACK=9MHz)
1.8 - 2.0 vp.p
2001 -06-1 9
TOSHIBA TC9083N/F
PACKAGE DIMENSIONS
SDIP42-P-600-1.78 Unit : mm
"is' CD
____‘L , In
--. ‘V
, 38.5MAX
", 38.0i0.2 f
cu. (a
, qi-r.
, “2 a
COVL mt , trt
G era'
1.22TYP
Weight : 4.13g (Typ.)
24 2001-06-19
TOSHIBA TC9083N/F
PACKAGE DIMENSIONS
QFP80-P-1420-0.80A Unit : mm
1 . OTYP
, F :i
3.05MAX
0.2i0.1
l i 1.2i0.2
Weight : 1.69 (Typ.)
25 2001-06-19
TOSHIBA TC9083N/F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
26 2001-06-19
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