TC7SPN3125TU ,Dual-supply level shifterTC7SPN3125TU/WBG TOSHIBA Digital Integrated Circuit Silicon Monolithic TC7SPN3125TU, TC7SPN3125WBG ..
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TC7SPN3125TU
Dual-supply level shifter
TC7SPN3125TU/WBG
TOSHIBA Digital Integrated Circuit Silicon Monolithic
TC7SPN3125TU, TC7SPN3125WBG Low Voltage / Low Power 1-Bit Dual Supply Bus Buffer
The TC7SPN3125 is an advanced high-speed CMOS 1-bit
dual supply voltage interface bus buffer fabricated with silicon
gate CMOS technology.
It is also designed with over voltage tolerant inputs and
outputs up to 3.6 V.
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,
or 2.5-V bus and a 1.8-V, 2.5-V or 3.3-V bus in mixed 1.2-V,
1.5-V, 1.8-V or 2.5-V/1.8-V, 2.5-V or 3.3-V supply systems.
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V
bus, the B-output with the 1.8-V, 2.5-V, 3.3-V bus.
The enable input (OE ) can be used to disable the device so
that the signal lines are effectively isolated.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features (Note) Level converter for interfacing 1.2-V to 1.8-V, 1.2-V to 2.5-V, 1.2-V to 3.3-V, 1.5-V to 2.5-V, 1.5-V to 3.3-V, 1.8-V
to 2.5-V, 1.8-V to 3.3-V or 2.5-V to 3.3-V system. High-speed operation : tpd = 13.7 ns (max) (VCCA = 2.5 ± 0.2 V, VCCB = 3.3 ± 0.3 V) tpd = 14.8 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V) tpd = 16.0 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 3.3 ± 0.3 V) tpd = 29 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 3.3 ± 0.3 V) tpd = 18.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.5 ± 0.2 V) tpd = 19.7 ns (max) (VCCA = 1.5 ± 0.1 V, VCCB = 2.5 ± 0.2 V) tpd = 33 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 2.5 ± 0.2 V) tpd = 43 ns (max) (VCCA = 1.2 ± 0.1 V, VCCB = 1.8 ± 0.15 V) Output current : IOHB / IOLB = ±3 mA (min) (VCCB = 3.0 V) IOHB / IOLB = ±2mA (min) (VCCB = 2.3 V) IOHB / IOLB = ±0.5 mA (min) (VCCB = 1.65 V) Latch-up performance: -300 mA ESD performance: Machine model ≥ ±200 V
Human body model ≥ ±2000 V Ultra-small package: UF6, WCSP6 Low current consumption : Using the new circuit significantly reduces current consumption when OE = “H”.
Suitable for battery-driven applications such as PDAs and cellular phones. Floating A-bus is permitted. (when OE = “H”) 3.6-V tolerant function and power-down protection provided on all inputs and outputs.
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
Weight
UF6: 0.007 g (typ.)
S-WFBGA6-0102-0.40A01: 0.001 g (typ.)
