TC55V2161FTI-85L ,131,072 WORD BY 16 BIT STATIC RAMTOSHIBA TC55V2161FTl-85,-10,-85L,-1OL131,072-WORD BY 16-BIT STATIC RAMThe TC55V2161FTI is a 2,097 , ..
TC55V328BFT-15 ,32,768 WORD-8 BIT STATIC RAMTOSHIBA TC55V328BJ/BFT-12,-1532,768-WORD BY 8-BIT CMOS STATIC RAMThe TC55V328BJ/BFT is a 262,144-bi ..
TC55V328BJ-12 ,32,768 WORD-8 BIT STATIC RAMTOSHIBA TC55V328BJ/BFT-12,-1532,768-WORD BY 8-BIT CMOS STATIC RAMThe TC55V328BJ/BFT is a 262,144-bi ..
TC55V328BJ-15 ,32,768 WORD-8 BIT STATIC RAMTOSHIBA TC55V328BJ/BFT-12,-1532,768-WORD BY 8-BIT CMOS STATIC RAMThe TC55V328BJ/BFT is a 262,144-bi ..
TC55V4000ST-70 ,524,288-WORD BY 8-BIT FULL CMOS STATIC RAMfeatures using CE • Data retention supply voltage of 1.5 to 3.6 V Access Time 70 ns 85 ns • Direct ..
TC55V4000ST-85 ,524,288-WORD BY 8-BIT FULL CMOS STATIC RAMTC55V4000ST-70,-85 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT ..
TC93P27F ,DTS Microcontroller (DTS-21)TC93P27F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC93P27F DTS Microcontroller ..
TC9400CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400F ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH A BUILT-IN 8-TIMES OVER SAMPLING DIGITAL FILTER/DIGITAL ATTENUATORTC94OOF/NT(‘annF T(annNI Slit'--.---- ' I Slit'--.---."E-A MODULATION SYSTEM DA CONVERTER WITH A BU ..
TC9402CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9402CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC55V2161FTI-85L
131,072 WORD BY 16 BIT STATIC RAM
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC55V2161FTI is a 2,097,152-bit static random access memory (SRAM) organized as 131,072 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7
to 3.6V power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz and a minimum cycle time of 85 ns. It is automatically laced in low-power mode at 1 pA
standby current (for the L-Version VDD = 3V, Ta = 25°C) when chip enable ( E) is asserted high or chip select
(CS) is asserted low. There are three control inputs. CE is usetioseleet the device and for data retention
control, CS isilsechor data retention control, and output enable (OE) provides fast memory access. Data byte
control pin (LB, UB) provides lower and upper byte access. This device is well suited to various microprocessor
system applications where high speed, low power and battery backup are required. And, with a guaranteed
operating range of -40'' to 85°C, the TC55V2161FTI can be used in environments exhibiting extreme
tergperature conditions. The TC55V2161FTI is available in a plastic 44-pin thin-small-outline package
(T OP).
FEATU RES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 10.8 mW/MHz (typical) TC55V2161FTI
0 Single power supply voltage_pf 2.7 to 3.6V -85, -85L -10, -10L
0 Power down features using CE and CS Access Time 85 ns 100 ns
0 Data retention supply voltage of 2 to 3.6V E Access Time 85 ns 100 ns
I Direct TTL compatibility for all inputs and outputs tN Access Time 45 n 50 n
0 Wide operating temperature range of -40" to 85°C s s
0 Standby current(maximum) q Package:
-85,-10 -85L,-10L
3.6V 60 prA 40 11A
3.0V 50 #A 30 #A
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
A4 L IO 44 JA5 A0 to A16 Address Inputs
A3 I: 2 43 3 A6 - .
A1 E 4 41 1E CS Chip Select Input
A0 E 5 40 l UB .
E E 6 39 :1 E 'e Read/Write Control Input
I/OI E 7 38 JIIO16 OE Output Enable Input
I/O2 E 8 37 g I/O15 E,W Data Byte Control Inputs
l/O3 9 36 |/O14
I/O4 E 10 35 Jl/O13 l/OI to |/O16 Data Inputs/Outputs
VDD E 11 34 3 GND VDD Power
GND L 12 33 J VDD GND Ground
|/05 E 13 32 J l/O12 NC N C .
IIO6 E 14 31 3 1/011 o onnectlon
I/O? E 15 30 3 I/O10
IIO8 L 16 29 J I/O9
W L 17 28 3 CS
A15 E 18 27 J A8
A14 C 19 26 3 A9
A13 E 20 25 3 A10
A12 E 21 24 :1 A11
A16 E 22 23 3 NC
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-12-15 1/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
BLOCK DIAGRAM
MEMORY
CELL ARRAY A-o GND
2,048 x 64 x 16
(2,097,152)
DECODER
BUFFER
OUTPUT
BUFFER
SENSE AMP
COLUMN
DECODER
OUTPUT
BUFFER
COLUMN CE
CLOCK ADDRESS BUFFER (cs)
GENERATOR
A15 A13 A16
A14 A12 A11
CE (CS)
OPERATING MODE
MODE E cs to-E RNV E W l/OI to l/O8 I/O9 to I/O16 POWER
L L Door Door IDDO
Read L H L H H L High-Z DOUT boo
L H DouT High-Z IDDO
L L DIN DIN IDDO
Write L H X L H L High-Z DIN boo
L H Dm: High-Z IDDO
H H x X
Output Deselect L H High-Z High-Z IDDO
CS Standby x L x x x x High-Z High-Z loos
Standby H x x x x X High-Z High-Z IDDS
Note: x = don't care. H= logic high. L= logiclow
1997-12-15 2/10
TOSHIBA
TC55V2161FTl-85,-10,-85L,-10L
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 4.6 V
VlN Input Voltage - 0.3 * to 4.6 V
VI/O Input/Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 0.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg Storage Temperature - 55 to 150 ''C
Topr Operating Temperature - 40 to 85 'C
* - 3.0 V when measured at a pulse width of 30 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 2.7 - 3.6 V
" Input High Voltage 2.2 - VDD + 3.6 V
Ihr, Input Low Voltage - 0.3 * - 0.6 V
VDH Data Retention Supply Voltage 2.0 - 3.6 V
* - 3.0 V when measured ata pulse width of 30 ns
DC CHARACTERISTICS (Ta =
-400 to 85°C,VDD = 2.7 to 3.6V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
u. Input Leakage Current VIN = 0V to VDD - - i 1.0 psA
lor, Output High Current VOH = VDD - 0.5V -0.5 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
E: " or CS--vm or MN-- "
|Lo Output Leakage Current VOUT = 0V to VDD - - + 1.0 prA
E v dCS v d VDD--- T I min - - 55
- ILan - IH an 31/* 10% cycle 1,15 - - IO
|DDO1 MN = " and IOUT = 0mA . 60
Other Input = V N VDD = Tc cle mm - -
. IH IL 3.3V i 0.3V y Irs - - 12
Operating Current - . mA
IDDOZ CE = 0.2V and VDD = Tcycle mm - - 45
CS=VDD-0.2V and 31/* 10% 1/15 - - 5
MN = VDD - 0.2 V, IOUT = 0mA VDD = T I min - - 50
Other Inputs = VDD - 0.2 V/0.2V 3.3V i 0.3V cyc e Irs - - 6
|DDS1 E = " or cs = " - - 2 mA
T 2 °c -85,-1O - 1 2.5
VDD = a-- 5 -85L,-10L - 0.5 1.2
3V i 10% o a -85, -10 - - 55
Ta-- -40 to85''C -85L,-10L - - 35
T 25°C -85,-10 - 1.5 3
DDS2 tan y urrent 3.3V :0.3V 0 a - ,- - -
(Note) or cs = 0.2 V Ta - - 40 to 85 C -85L, -10L - - 40 ,uA
VOD-- 2.0 to 3.6V t? -85, -10 - 1 2
Ta=25 C -85L,-10L - 0.5 1
o a -85,-1o - - 5
Von =3V Ta = -40 to 40 C -85L,-1OL - - 3
T 4 a 5°C -85,-10 - - 50
a-- - 0 ms -85L,-10L - - 30
Note: In standby mode with E: VDD-tMV, these limits are assured for the condition Cr-ei- 0.2V or CSS0.2V.
1997-12-15 3/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
CAPACITANCE (Ta = 25°C,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
1997-12-15 4/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 2.7 to 3.6V)
READ CYCLE
TC55V2161FTI
SYMBOL PARAMETER -85, -85L -10, -10L UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 85 - 100 -
tACC Address Access Time - 85 - 100
tco Chip Enable Access Time - 85 - 100
toe Output Enable Access Time - 45 - 50
tBA Data Byte Control Access Time - 45 - 50
tcos Chip Enable Low to Output Active 5 - 5 -
tOEE Output Enable Low to Output Active 0 - 0 - ns
tBE Data Byte Control Low to Output Active 0 - 0 -
too Chip Enable High to Output High-Z - 35 - 40
tooo Output Enable High to Output High-Z - 35 - 40
tBDO Data Byte Control High to Output High-Z - 35 - 40
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55V2161FTI
SYMBOL PARAMETER -8S, -85L -10, -10L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 60 - 60 -
tcw Chip Enable to End of Write 75 - 80 -
tsw Data Byte Control to End of Write 60 - 60 -
tas Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
toow R/W Low to Output High-Z - 35 - 40
togw R/W High to Output Active 0 - 0 -
tDS Data Setup Time 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.4 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, W: 5 ns
1997-12-15 5/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
TIMING DIAGRAMS
ADDRESS
DOUT VALID DATA OUT
IND ERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
DOUT (See Note 2) (See Note 3)
tos to
Dm (See Note 5) VALID DATA IN (See Note 5)
1997-12-15 6/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
WRITE CYCLE 2 LEE- CONTROLLED) (See Note 4)
ADDRESS
DlN (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (trt5, fB‘ CONTROLLED) (See Note 4)
ADDRESS X X
tas twp tum
CE _ 2
W,t7 ' "N /
tos tDH
DIN (See Note 5) kt VALID DATA IN 8 (See Note 5) 8
1997-12-15 7/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CE goes LOW (or CS goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If tTIT goes HIGH (or CS goes LOW) coincident with or before R/W goes HIGH, the outputs
will remain at high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = ty' to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 3.6 V
-85, -10 - - 5
Ta = - 40° to 40°C
- L, -1 L - -
VDD = 3.0V 85 0 3
-85, -10 - - 50
bose Stand by Current Ta = - 40'' to 85''C #A
-85L, -10L - - 35
-85, -10 - - 60
VDD = 3.0V Ta = - 40° to 85°C
-85L, -10L - - 45
ttcm Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
tTE CONTROLLED DATA RETENTION MODE (See Note 1)
VDD ) DATA RETENTION MODE
2.7 V - - - - - ----_
(See Note 2) (See Note 2)
" --- l /
- / VDD - 0.2V
CE tCDR _ tit
1997-12-15 8/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
CE CONTROLLED DATA RETENTION MODE (See Note 3)
VDD CC") DATA RETENTION MODE hi,
2.7 v ---------'..------------------------i.---------
" tCDR tR
V - - - -
IL k , 0.2 v V
Note: (1) In CE controlled data retention mode, minimum standby current mode is entered when
CS s 0.2V0r CS 2 VDD - 0.2V.
(2) When C-E is operating at the VIH level (2.2 V), the operating current is given by 1DDSl
during the transition of VDD from 3.6 to 2.4 V.
(3) In CS controlled data retention mode, minimum standby current mode is entered when
CS s 0.2 V.
1997-12-15 9/10
TOSHIBA TC55V2161FTl-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOPII 44-P-400-O.80)
Units in mm
‘HHHHHHHHHHHHHHHHHHHHHH r
10.16i0.1
11.76i0.2
l"""''" HHHHH
O'aio'osm
I 18.81 MAX
" 18.41101
1.0i0.1
1 2MAX
0.15:?)95
0.5i0.1
Weight: (typ)
1997-12-15 10/10
www.ic-phoenix.com
.
