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TC55V1864FT-15 |TC55V1864FT15TOSHIBA ?N/a40avai65,536-WORD BY 16-BIT CMOS STATIC RAM
TC55V1864J-15 |TC55V1864J15TOSN/a37avai65,536-WORD BY 16-BIT CMOS STATIC RAM


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TC55V1864FT-15-TC55V1864J-15
65,536-WORD BY 16-BIT CMOS STATIC RAM
TOSHIBA TC55V1864J/FT-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
65,536-WORD BY18-BIT CMOS STATIC RAM
D E SC RI PT I O N
The TC55V1864J/FT is a 1,17 9,648-bit high-speed static random access memory (SRAM) organized as 65,536
words by 18 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed,
and low-voltage operation it operates from a single 3.3 V power supply. Chip enable (CE) can be used to place
the device in a low-power mode, and output enable (OFT) provides fast memory access. Data byte control signals
(LB, UB) provide lower and upper byte access. This device is well suited to cache memory applications where
high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible.
The TC55V1864J/FT is available in plastic 44-pin SOJ and TSOP packages (400 mil width) for high density
surface assembly.
FEATURES
tt Fast access time of 15 ns (maximum) 0 Single power supply voltage of 3.3 i 0.3 V.
0 Low-power dissipation 0 Fully static operation
(the following are maximum values) 0 All inputs and outputs are LVTTL compatible
Cycle Time 15 20 30 ns 0 Output buffer control using OE
Operation (max) 200 180 150 mA 0 Data byte control using LB (101 to 109) and UB
Standby: 2 mA (1010 to 1018)
0 Packages:
SOJ44-P-400-1.27 (J ) (Weight: 1.64 g typ)
TSOP ll 44-P-400-0.80 (FT) (Weight: 0.45 g typ)
PIN ASSIGNMENT PIN NAMES
A4 E 1 44 JA5 A4 1: 1° 44 = A5 l/OI t:l/018 Data Inputs/Outputs
A3 E 2 43 Cl A6 tl I: g fd = A6 CE Chip Enable
A = 4 = A7 - .
12 " 2? 3% A1 = 4 41 = E VI_/E Write Enable Input
A0 E 5 40 JW A_OIZ 5 40 = WB OE Output Enable
E E 6 39 :1 E ' E , 3593 ==', b018 7 W Data Byte Control Inputs
l/OI L 7 38 3 V018 1/02 1: 8 E 37 = 1/017 Voo Power (o 3.3V)
1/02 L 8 ' 37 31/017 1/03 = 9 m 36 = 1/016 d
1/03 L 9 w 36 11/016 1/041: 10 - 35 211/015 GND Groun
I/O4 L 10 , 35 II l/O15 VDD I: 11 > 34 = GND NU Not Used (Input)
VDDEH 34 JGND GND:12 33:1v
GNDE 12 I 33 JVryry "82': 13 t 32 = 1/81431
I L13O323I/O14 V =14 1=1l/O1
1:82 L "d I- 31 3 (fill 1/07: 15 tit 30 211/012
1/071: 15 V 30 :11/012 ”08': 16 29 = l/O11
1/0_9= 17 28 21/010
|/08E 16 29 II 1/011 WE =18 27 = NU
|/O_9|:17 28JIIO10 A15|=19 26=1A8
WEE 18 27 ZINU A14|ZZO 25 :1A9
A151: 19 2621A8 A13|=21 24=A1o
A14E 20 25 :IA9 A12I=22 23 =A11
A13 E 21 24 :1 A10
A12 E 22 23 :1 A11
(SOJ) (TSOP)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-18 1/10
TOSHIBA TC55V1864J/FT-15
BLOCK DIAGRAM
E H VDD
MEMORY
03 CELL ARRAY t GND
256x256x 18
Iffy, (1,179,648)
E582 5 CE 'G a
I/O5 t: < n. u,
I/D6 D I- F- LL
I/O7 m < Q 3
E783 thQ
l/O10 SENSE AMP.
US}; F c:
I/o13 F- w < a tl
llO14 D l _ '- LL
l/O15 g: COLUMN <33
iggig - m DECODER tCt O m
COLUMN
CLOCK ADDRESS BUFFER
GENERATOR A0 A2 A12 A14
A1 A11 A13 A15
MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT
VDD Power Supply Voltage - 0.5-4.6 V
" Input Terminal Voltage - 0.5 * -4.6 V
VI/o Input/Output Terminal Voltage - 0.5 * ~VDD + 0.5** V
Po Power Dissipation 1.2 W
Tsolder Soldering Temperature (10s) 260 T
Tstrg Storage Temperature - 65-150 ''C
Top, Operating Temperature - 10~85 ''C
: -1.5V with a pulse width of 20% . tRC min (4ns max)
** : VDD+1.5V with a pulse width of 20% . tRC min (4ns max)
1997-06-18 2/10
TOSHIBA
TC55V1864J/FT-15
DC RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDD Power Suply Voltage 3.0 3.3 3.6 V
VlH Input High Voltage 2.0 - VDD + 0.3** V
" Input Low Voltage -0.3* - 0.8 V
* : -1.0V with a pulse width of 20% . tRC min (4ns max)
** : VDD+1.0V with a pulse width of 20%-tRC min(4ns max)
DC and OPERATING CHARACTERISTICS (Ta = o--7ty'c, VDD = 3.3V i 0.3V)
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
I Input Leakage Current V 0 V 1 1
IL (Except NU pin) IN" DD psA
k E=V|H or WE=V|L or Oi-uw.,
lLo Output Lea age Current VOL”: 0~VDD - 1 - 1 ,A
I Input Current VIN = 0~0.8V - 1 - 20
I(NU) (NU pin) VIN = 0~0.2V - 1 - 1 psA
IOH = - 2mA 2.4 - -
VOH Output High Voltage
loH-- -100pA Voce0.2 - - V
lor. = 2mA - - 0.4
VOL Output Low Voltage
IOL = 100,1A - - 0.2
CE=VI, lout=0mA tcycle=15ns - - 200
I DDO Operating Current tcycle = 20ns - - 180 mA
Other Inputs=Vm/1hL tcycle=30ns - - 150
|DDs1 E=VIH, Other |nputs=V.H/V.L - - 20
l Standby Current E: VDD - 0.2V 2 mA
DDS 2 Other Inputs = VDD - 0.2V or 0.2V - -
CAPACITANCE (Ta = 25°C, f =1.0MHZ)
SYMBOL PARAMETER TEST CONDITION MAX. UNIT
ClN Input Capacitance VIN = GND 6 pF
CI/o Input/Output Capacitance VI/o = GND 8 pF
NOTE : This parameter is periodically sampled and is not 100% tested.
1997-06-18 3/10
TOSHIBA
TC55V1864J/FT-15
OPERATING MODE
OPERATING MODE CE OE WE LB UB llO1~|/09 IIO10~IIO18 POWER
L L Output Output IDDO
Read L L H H L High Impedance Output IDDO
L H Output High Impedance IDDO
L L Input Input IDDO
Write L * L H L High Impedance Input IDDO
L H Input High Impedance IDDO
L H H * *
Output Disable High Impedance High Impedance IDDO
L * * H H
Standby H * * * * High Impedance High Impedance IDDS
*:HorL
NOTE : N.U. pin must be kept open electrically or pulled down to GND level or less than 0.8V.
Applying a voltage more than 0.8V to N.U. pin is prohibited.
1997-06-18 4/10
TOSHIBA
AC CHARACTERISTICS (Ta = 0--7ty'C (1), VDD = 3.3V , 0.3V)
TC55V1864J/FT-15
READ CYCLE
SYMBOL PARAMETER TC55VI864J/FT - 15 UNIT
MIN. MAX.
tRc Read Cycle Time 15 -
tacc Address Access Time - 15
tco E Access Time - 15
tog E Access Time - 8
tBA U3: CIT Access Time - 8
tOH Output Data Hold Time from Address Change 3 -
tcos Output Enable Time from E 3 - ns
tOEE Output Enable Time from ty-E 1 -
tBE Output Enable Time from UB, E 1 -
tCOD Output Disable Time from "ell'" - 8
tODO Output Disable Time from o-E - 8
tsp Output Disable Time from W, E - 8
WRITE CYCLE
TC55V1864J/FT - 15
SYMBOL PARAMETER UNIT
MIN. MAX.
twc Write Cycle Time 15 -
twp Write Pulse Width 9 -
tcw Chip Enable to End of Write 12 -
th W, w Enable to End of Write 11 -
tAw Address Valid to End of Write 11 -
Us Address Set Up Time 0 - ns
tWR Write Recovery Time 0 -
tDs Data Set Up Time 8 -
tDH Data Hold Time 0 -
tOEw Output Enable Time from m 1 -
toow Output Disable Time from Th7g - 8
AC TEST CONDITIONS Ligd 3 V
Input Pulse Level 3.0V/0.0V
Input Pulse Rise and Fall Time 3ns 12000
. . IIO Zo--50n IIOpin
Input Timing Measurement 1.5V
Reference Level RL = 500 CL-- 5pF 8700
Output Timing Measurement 1.5V cFa”; ;
Reference Level h-- 1.5V (For tcos, tOEE: tcoo,
Output Load Fig. 1 tooo, toew and toow)
1997-06-18 5/10
TOSHIBA TC55V1864J/FT-15
TIMING WAVEFORMS
READ CYCLE (2)
ADDRESSES
tse (6)
tOEE (6)
Dout OUTPUT DATA VALID
tcoe (6)
tso (6)
WRITE CYCLE 1 (5) (TCE Controlled)
ADDRESSES X X
tAs twp ’ tWR
m k _ i!
E A, /
UEEE /
tosw 6)
High Impedance
Dout (4)
I tDs toc
Din )k DATA IN STABLE X
1997-06-18 6/10
TOSHIBA
WRITE CYCLE 2 (5) (ttE Controlled)
TC55V1864J/FT-15
ADDRESSES X X
tAS twe twa
W \R 2/
_E E R f
mm "N tr"
bel6 t (6)
Dout tcos(6) 9 High Impedance
"tr-YS-tr-YH,
Din *DATA IN STABLEJK
WRITE CYCLE 3 (5) (W, 1-}? Controlled)
ADDRESSES X X
tAS twp twp:
m \ 2%
E _ [y
W,t7 -iis, _, /
tco; )
tsE(6), t0Dw(6)
Dout High Impedance
etc-rs-tr-YH,
Din *DATA IN STABLE*
1997-06-18 7/10
TOSHIBA TC55V1864J/FT-15
NOTE :
1. The operating temperature (Ta) is guaranteed with transverse air flow exceeding 400 linear
feet per minute.
2. WE is High for Read Cycle.
3. Assuming that CE Low transition occurs coincident with or after WLOW transition, Outputs
remain in a high impedance state.
4. Assuming that "tTri")" High transition occurs coincident with or prior TirtT High transition,
Outputs remain in a high impedance state.
5. Assuming that tTE is High for Write Cycle, Outputs are in a high impedance state during this
period.
6. These parameters are specified as follows and measured by using the load shown in Fig. 1.
(A) tCOE, tOEE, tBE, tOEW ...... Output Enable Time
(B) tCOD, tom), tBD, tonw ...... Output Disable Time
w, E rr
(A) (B)
_-_ --_
f j 0.2V
High Impedance I 0.2V High Impedance
Dom -, OUTPUT DATA VALID -
io.2v . - 0.2V
UNKNOWN UNKNOWN l
1997-06-18 8/10
TOSHIBA TC55V1864J/FT-15
OUTLINE DRAWINGS
Plastic SO) (SOJ44-P-400-1.27)
Unit in mm
10.16i0.12
11 OStO 12
9.3TYP
b-ll-lL-dl-jr-ll-JI-lL-ll-ji-lt-dt-JI-jr-lL-jr-It-IL-it-ir-dt-it-l
29.0MAX
28.58i0.12
Weight : 1.64g (Typ.)
1997-06-18 9/10
TOSHIBA TC55V1864J/FT-15
OUTLINE DRAWINGS
Plastic TSOP (TSOPII 44-P-400-0.80)
Unit in mm
'lflflflflflRflflfifl7ppgpilppg7p
'r"er1""""'1il.ls,ii, -
0.805TYP 0310.05
+ 0.13
1 18.81MAX
,- Q m
l 1B.41i0.1 E1 ii'.! .33?
Weight : g (Typ.)
1997-06-18 10/10

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