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TC55V16256FT-12-TC55V16256FT-15-TC55V16256J-12-TC55V16256J-15
262,144-WORD BY 16-BIT CMOS STATIC RAM
TC55V16256J/FT-12,-15 Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control using LB (I/O1 to I/O8) and
UB (I/O9 to I/O16) Package:
SOJ44-P-400-1.27 (J) (Weight: 1.64 g typ)
TSOP II44-P-400-0.80 (FT) (Weight: 0.45 g typ) TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT CMOS STATIC RAM
DESCRIPTION The TC55V16256J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable (CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. Data byte control signals (LB,UB ) provide lower and upper
byte access. This device is well suited to cache memory applications where high-speed access and high-speed
storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256J/FT is available in
plastic 44-pin SOJ and TSOP with 400mil width for high density surface assembly.
FEATURES Fast access time (the following are maximum values)
TC55V16256J/FT-12:12 ns
TC55V16256J/FT-15:15 ns Low-power dissipation
(the following are maximum values)
Standby:4 mA (both devices)
PIN ASSIGNMENT (TOP VIEW) PIN NAMES 44 PIN SOJ 44 PIN TSOP
I/O1
I/O2
I/O3
I/O4
VDD
GND
I/O5
I/O6
I/O7
I/O8
A15
A14
A13
A12
A16
A5
A6
A7
I/O16
I/O15
I/O14
I/O13
GND
VDD
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17
22 23
I/O1
I/O2
I/O3
I/O4
VDD
GND
I/O5
I/O6
I/O7
I/O8
A15
A14
A13
A12
A16
A5
A6
A7
I/O16
I/O15
I/O14
I/O13
GND
VDD
I/O12
I/O11
I/O10
I/O9
NU
A8
A9
A10
A11
A17 CE
