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TC55V1001F-10-TC55V1001F-85-TC55V1001SR-10-TC55V1001ST-10-TC55V1001TR-10
131,072 WORD BY 8 BIT STATIC RAM
TOSH I BA TC55V1001 F/FT/TR/ST/SR-85,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 8-BIT STATIC RAM
D E SC R I PT I O N
The TC55V1001F/FT/TR/ST/SR is a 1,048,576-bit static random access memory (SRAM) organized as 131,072
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 2.7 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an
operating current of 3 mA/MHz (typ) and a minimum cycle time of 85 ns. It is automatically placed in low-
power mode at 1 PA standby current (typ) when chip enable (GET) is asserted high or (CE2) is asserted low.
There are three control inputs. m and CE2 are used to select the device and for data retention control, and
output enable (UE) provides fast memory access. This device is well suited to various microprocessor system
applications where high speed, low power and battery backup are required. The TC55V1001F/FT/TR/ST/SR is
available in a plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin thin-
small-outline package (TSOP).
FEATU RES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 10.8 mW/MHz(typical) 2.7 to 3.6V
0 Standby current of 3 pdt (maximum) at -85 -10
Ta = 25°C Access Time 85 ns 100 ns
0 Single power supply voltage of 2.7 to 3.6 V CE1 Access Time 85 ns 100 ns
0 Power down features using CE1 and CE2. - Access Time 85 ns 100 ns
0 Data retention supply voltage of 2 to 3.6 V OE Access Time 45 ns 50 ns
o Direct TTL compatibility for all inputs and qt Packages:
out uts SOP32-P-525-L27(F) (Weight:1.04gtyp)
p TSOP I 32-P-0820-0.50(FT) (Weight:0.34gtyp)
TSOP I 32-P-0820-0.50A (TR) (Weight: 0.34 gtyp)
TSOP I 32-P-0.50 (ST) (Weight: 0.24 gtyp)
TSOP I 32-P-0.50A (SR) (Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
o 32 PIN SOP o 32 PIN TSOP
V 32 El V (Normal pinout) (Reverse pinout)
31% E 2 31 El Jd?
A14 l: 3 303 CE2
A12 I: 4 29:1 R/W
A7 C 5 283 A13
A6 E 6 27:I A8
A5 E 7 26: A9
A4 E 8 25:1 Alf
A3 1: 9 24:I OE
A2 E 10 23:! Alll
A1 |: 11 22:| CE1
A0 c 12 213 l/O8
l/OI 1: 13 20: I/O?
I/O2 E 14 133 :18?
113332 173104
PIN NAMES
A0 to A16 Addressllnputs PinNo. 1 2 3 4 5 6 7 8 9 IO 11 12 13 14 15 16
R’_W Read/Write Control PinName A11 As N A13 R/W CE2 A15 VDD NC A16 A14 A12 A7 As As A4
OE Output Enable .
c? CE2 Chip Enable Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1/01 to 1/08 Data Iroput/Output Pin Name As A2 A1 Ao 1/01 1/02 1/03 GND AM I/OS l/O6 1/07 l/O8 c? Am E
VDD Power
GND Ground
NC No Connection
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-20 1/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-10
BLOCK DIAGRAM
A7 --o Voo
£3 a a 3: A-o GND
A10 g Em ii' MEMORY CELL
m; en: 0E 05 ARRAY
A13 5tt <2 S?, 1024x128x8
jyf, iii, iig ti?, (1048576)
A16 real rere tECI
l/OI SENSEAMP
COLUMN ADDRESS
t COLUMNADDRESS
I/08 02
AOA1A2 A3 A4 A5 A6
OPERATION MODE
MODE l/OI to l/O8
Read DOUT
Write DIN
Outputs Disabled H High-Z
H x x High-Z
Standby .
x x x Hi h-Z
Note: x = don'tcare. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 4.6 V
" Input Voltage - 0.3* to 4.6 V
VI/o Input/Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 0.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg. Storage Temperature - 55 to 150 ''C
Topr. Operating Temperature 0 to 70 ''C
* - 3.0 then measured ata pulse width of 50 ns ** SOP
1997-06-20 2/13
TOSHIBA
TC55V1001F/FT/TR/ST/SR-85,-10
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0°
SYMBOL
PARAMETER MIN
- 0.3*
- 3.0 V when
Power Supply Voltage
Input High Voltage
In Low Vol
Data Retention Su Volta
to 70°C)
2.7 to 3.6 V
VDD + 0.3
measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = ty' to 70°C, VDD = 2.7 to 3.6 V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VIN = 0V to VDD - - i 1.0 #A
IOH Output High Current VOH = VDD - 0.5V - 0.5 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
m = VIH or CE2 = " or W = VIL or
- - - +
ILO Output Leakage Current OE = VIH, VOUT = 0V to VDD - 1.0 #A
VDD = T l min - - 35
- - - c c e
CEI= Ihr. and CE2 - VIH and 3V i10% y IM; - - 10
|DDO1 W = VIH, |OUT = 0 mA .
VDD = mm - - 40
Other Input = VlH/VIL Tcycle
3.3V i 0.3V IM; - - 12
Operating Current 7 . mA
CE1 = 0.2V and VDD = Tcycle mIn - - 30
I CE2=Voo-0.2V 3V* 10% I/s - - 5
DDO2 R/W = Voo - 0.2V, IOUT = 0 mA VDD = min - - 35
Other Inputs = VDD - 0.2 V/0.2V 3_3v i 0.3V Tcycle 1 M; - - 6
IDDS'I i = " or CE2 = VIL - - 2 mA
Voo = Ta = 25°C - 1 2
3V , 10% Ta = O" to 70°C - - 20
IDDSZ Standby Current a = VDD - 0.2V VDD = Ta = 25°C - 2 3
(Note) or CE2 = 0.2V 3.3V , 0.3V Ta = (Y' to 70°C - - 25 #A
VDD = 2.0 to 3.6V Ta = 25°C - 1 -
VDD = 3.0V Ta = J' to 40°C - - 3
Ta = (Y' to 70°C - - 15
Note: In standby mode with C? 2 VDD - 0.2 V, these limits are assured for the condition CE2 2 VDD - 0.2 V or CE2 s 0.2 V.
CAPACITANCE (Ta = 25oC,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 F
Cour Output Capacitance VQUT = GND 10
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-20 3/13
TOSH I BA TC55V1001 F/FT/TR/ST/SR-85,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 2.7 to 3.6 V)
READ CYCLE
TC55V1001 F/FT/TR/ST/SR
SYMBOL PARAMETER -85 -10 UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 85 - 100 -
tacc Address Access Time - 85 - 100
tco1 Chip Enable (m) Access Time - 85 - 100
tcoz Chip Enable (CE2) Access Time - 85 - 100
tOE Output Enable Access Time - 45 - 50
tcoE Chip Enable Low to Output Active 10 - 10 - ns
tOEE Output Enable Low to Output Active 5 - 5 -
too Chip Enable High to Output High-Z - 30 - 35
tooo Output Enable High to Output High-Z - 30 - 35
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55V1001F/FT/TR/ST/SR
SYMBOL PARAMETER -85 -10 UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 60 - 60 -
tcw Chip Enable to End of Write 75 - 80 -
tas Address Setup Time 0 - 0 -
tum Write Recovery Time 0 - 0 - ns
tODW RNV Low to Output High-Z - 30 - 35
toaw R/W High to Output Active 5 - 5 -
tog Data Setup Time 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.6 V, 2.2 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, W: 5 ns
1997-06-20 4/13
TOSHIBA
TIMING DIAGRAMS
TC55V1001F/FT/TR/ST/SR-85,-10
READ CYCLE (See Note 1)
ADDRESS X X
tacc Jor-i
CE2 / tcoz
_ tco1 '
CEI /%A y
tOE tOD
E N //
toss tong
Dom t VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
2/ tcw iF'"
toDw toew
(See Note 2) (See Note 3)
tos tDH
/(See Note 5) VALID DATA IN (See Note 5)
Wy,",",',',)',)",','',',,",',, A
1997-06-20 5/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-1O
WRITE CYCLE 2 (CEl CONTROLLED) (See Note 4)
ADDRESS X X
twe tWR
CE2 /// tcw NF"
tCOE A tODW
tos tDH
IAN (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4)
ADDRESS X X
AS twe tWR
MN % y
CE2 " s' tcw "t
C? % /
tcos tODW
tos tDH
DIN (See Note 5) VALID DATA IN (See Note 5)
1997-06-20 6/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-1O
Note: (1) ww remains HIGH for the read cycle.
(2) If CE1 goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If CE-I goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4) If tTIT is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 3.6 V
VDH = 3.0V - - 15*
'0032 Standby Current pzA
I/DH = 3.6V - - 25
tcrm Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
* 3 psA (max) at Ta = (Y' to 40°C
CE1 CONTROLLED DATA RETENTION MODE (See Note 1)
VDD ) DATA RETENTION MODE
2.7 V ------ - - - - q.-----------------.----------
(See Note 2) (See Note 2)
Ihr, - - - l /
- VDD - 0.2 V
CE1 tCDR tR
1997-06-20 7/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-1O
CE2 CONTROLLED DATA RETENTION MODE (See Note 3)
VDD —DD—\ DATA RETENTION MODE h=,
2.7V -----------d---
I/m N 4 tCDR tR
V - - -
IL tk, \\ 0.2V f"
Note: (1) In (El controlled data retention mode, minimum standby current mode is entered when
CE2 E 0.2 V or CE2 E VDD - 0.2V.
(2) When CEI is operating at the VIH level (2 V), the operating current is given by IDDSl
during the transition of VDD from 3.6 to 2.2 V.
(3) In CE2 controlled data retention mode, minimum standby current mode is entered when
CE2 E 0.2 V.
1997-06-20 8/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-1O
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
'ii?acsjuscasssv1a7----
10 7i0 2
14.13i0.3
11lil'jriljflilerjlC,-----i
0.775TYP 0.3i0.1
21.1 MAX
h 20.6i0.2 I
I . G.l.
2.8MAX
Weight: 1.049 (typ)
Units in mm
(525mil)
1997-06-20 9/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50)
TC55V1001F/FT/TR/ST/SR-85,-10
Units in mm
Weight: 0.349 (typ)
"gg32 N
El Gl.
112'', " Lo tD
"a"Ei' d
17 th.
18.4M.2 " E 1 0i0.1 0.1:005
20.0t0.2 co" 1 2MAX
0.5i0.
1997-06-20 10/13
TOSH I BA TC55V1001F/FT/TR/ST/SR-85,-1O
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50A)
Units in mm
j,sll'jz.5, 1 cu.
o n: o
JJZI I
II: k x
IC.', / co
ii-z' . ai
16 a.'
N 18.4uF0.2 - E 1 o¢o.1
20.0:02 ci 1.2MAX
0.5:0.
Weight: 0.349 (typ)
1997-06-20 11/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50)
TC55V1001F/FT/TR/ST/SR-85,-10
Units in mm
F 1313328 n
1% C) 11:: fl
EEC :31: g
E“: Tn: c;
:1: :13 r
DI; -urn < C
CIE: ZIIJ E o
LT/ Ee?, r ai
:11: -ret .
EEC IE I
:11: jirj,,I u
mag a 17
4 11Aeio.1 E ‘0‘1i0.05
" 1314-102 CD 41-2MAX
Weight: 0.249 (typ)
1997-06-20 12/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50A)
2 ”7 zsral ci
3 gt 1m +I
1:1: :03 a
:n: m 6
EU: :33 v
:1]: :n____:
El]: LILO
CIC :[E]
D]: I)
:1: H'“
Efr, an A
:n: In.
[j/f, tn: f/v?.
[:l]: :LLI
17:ka a_ .15.
113:01 _ E
Weight: 0.249 (typ)
TC55V1001F/FT/TR/ST/SR-85,-10
Units in mm
8.4MAX
0.1i0.05
1 1_2MAX
1997-06-20 13/13
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