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TC55V1001AFTOSN/a759avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AF-10 |TC55V1001AF10TOSHIBAN/a1400avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AF-10L |TC55V1001AF10LTOSHIBAN/a1400avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AF-85 |TC55V1001AF85TOSN/a1816avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AF-85L |TC55V1001AF85LTOSHIBAN/a1400avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AFT-85L |TC55V1001AFT85LTOSHIBAN/a172avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001AST-85L |TC55V1001AST85LTOSHIBAN/a16avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC55V1001ATR-85 |TC55V1001ATR85TOSHIBAN/a440avai131,072-WORD BY 8-BIT CMOS STATIC RAM


TC55V1001AF-85 ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC55V100 ..
TC55V1001AF-85L ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC55V100 ..
TC55V1001AFI-10 ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC55V1001AFI-10L ,131,072-WORD BY 8-BIT CMOS STATIC RAMapplications where high speed, low power and battery backup arerequired. The TC55V1001AFI/AFTI/ATRI ..
TC55V1001AFI-85 ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC55V1001AFI-85L ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC9312N ,Logic Controller LSI for Audio Systemapplications.. Programmable ROM Array construction. (PRA). Having 10 input, 10 output and 4 input/o ..
TC9314F-017 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9314F-026 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9314F-026 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9317F ,DTS MICROCONTROLLER (DTS-21)Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display. ..
TC9317F ,DTS MICROCONTROLLER (DTS-21)Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phasecomparison out ..


TC55V1001AF-TC55V1001AF-10-TC55V1001AF-10L-TC55V1001AF-85-TC55V1001AF-85L-TC55V1001AFT-85L-TC55V1001AST-85L-TC55V1001ATR-85
131,072-WORD BY 8-BIT CMOS STATIC RAM
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131 ,072-WORD BY 8-BIT STATIC RAM
D E S C R I PT I O N
The TC55V1001AF/AFT/ATR/AST/ASR is a 1,048,576-bit static random access memory (SRAM) organized as
131,072 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device
operates from a single 2.7 to 3.6 V power supply. Advanced circuit technology provides both high speed and
low power at an operating current of 3 mA/MHz and a minimum cycle time of 85 ns. It is automatically placed
in low-power mode at 0.5 PA standby current (L-Version at VDD = 3V, 'I_‘a_=_25°C) when chip enable (CET) is
asserted high or (CE2) is asserted low. There are three control inputs. CEI and CE2 are used to select the
device and for data retention control, and output enable (0Tif) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are
required. The TC55V100lAF/AFT/ATR/AST/ASR is available in a plastic 32-pin small-outline package (SOP)
and normal and reverse pinout plastic 32-pin thin-small-outline package (TSOP).
FEATURES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 10.8 mW/MHz (typical) TC55V1001AF/AFT/ATR/AST/ASR
0 Single power supply voltage of2.7 to 3.6V -85, -85L _ 10, _ 10L
0 Power dowrt features using CEI and CE2. Access Time 85ns 100ns
0 Data retention supply voltage of 2 to 3.6 V W Access Time 85ns 100ns
0 Direct TTL compatibility for all inputs and .
outputs E Access Time 85ns 100ns
It Standby current(Ta=25°C maximum) OE Access Time 45ns 50ns
TC55V1001AF/AFT/ATR/AST/ASR qt Packages: .
-85 -10 -85L -10L SOP32-P-525-1.27 (AF) (Weight: 1.04 gtyp)
' ' TSOP I 32-P-0820-0.50 (AFT) (Weight: 0.34 gtyp)
3.6V 3% os prA TSOP I 32-P-0820-0.50A(ATR) (Weight:0.34gtyp)
3.0V 1 FA 0.5 prA TSOP I 32-P-0.50 (AST) (Weight: 0.24 g typ)
TSOP I 32-P-0.50A (ASR) (Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
0 32 PIN SOP o 32 PIN TSOP
NC I: 1 V 3221 V (Normalpinout) (Reverse pinout)
A16 1: 2 31 El A13
A14 1: 3 303 CE2
A12 1: 4 293 RM 16 1
A7 1: 5 28:1 A13
A6 1: 6 27D A8
A5 I: 7 26D A9
A4 1: 8 255 A_11
A3 |: 9 24:l OE
A2 1: 10 233 A_10
A1 I: 11 22:l CE1
A0 c 12 21 El I/O8
1/01 I: 13 20: l/OT
I/O2 E14 13% 118% n 32
tls/fe/z, 1112 17:! l/OI
PIN NAMES
A0 to A16 Address .Inputs Pin No. 1 2 3 4 5 6 7 8 9 IO 11 12 13 14 15 16
RM Read/Write Control Pin Name A11 A9 N A13 R/W CE2 A15 VDD NC A16 A14 A12 A7 As As A4
OE Output Enable .
m, CE2 Chip Enable Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 2 31 3
l/Ol to l/O8 Data Input/Output Pin Name A3 A2 A1 A0 1/01 1/02 1/03 GND 1/04 1/05 I/06 1/07 l/O8 CE1 A10 OE
VDD Power
GND Ground
NC No Connection
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-03-17 1/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
BLOCK DIAGRAM
A4 -o VDD
£2 a a a --o GND
A7 'tl :1: E MEMORY CELL
shul ga, SE fit ARRAY
A13 ft' " if?, 1024x128x8
/hlt 55 tg y? (1048576)
A16 tern ttctts cm
I/OI SENSEAMP
d COLUMNADDRESS
, f/ir, s
m, t COLUMNADDRESS
l/O8 8;
dll) COLUMNADDRESS
A0 A2 A9 All
A1 A3 A10
OPERATION MODE
MODE W CE2 E MN I/OI to l/O8 POWER
Read L H L H DOUT IDDO
Write L H X L DIN IDDO
Outputs Disabled L H H H High-Z IDDO
H x x x High-Z IDDS
Standby .
X L X X High-Z IDDS
Note: x = don't care. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 4.6 V
" Input Voltage - 0.3* to 4.6 V
VI/o Input/Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 0.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg. Storage Temperature - 55 to 150 T
Topr. Operating Temperature 0 to 70 "C
* - 3.0 V when measured at a pulse width of 50 ns ** SOP
1998-03-17 2/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
2.7 to 3.6V
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 2.7 - 3.6
" Input High Voltage 2.0 - VDD + 0.3 V
" Input Low Voltage - 0.3* - 0.8
VDH Data Retention Supply Voltage 2.0 - 3.6
* - 3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 2.7 to 3.6 V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
In. Input Leakage Current VIN = 0V to VDD - - i 1.0 psA
10H Output High Current VOH = VDD - 0.5V -0.5 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
lLo Output Leakage Current %1:V\ll:j C7, Zylioozlglpw = " or - - i 1.0 prA
7 VDD = min - - 35
CE1 = vIL and CE2 = VlH and 3V , 10% Tcycle m - - 10
'0001 MN = ve, IOUT = 0 mA VDD = min - - 40
Other Input = VIHNIL 3.3V i 0.3V Tcycle 1/15 - - 12
Operating Current . mA
m = 0.2v and VDD = Tcycle mm - - 30
CE2--VDD-0.2V 3V1 10% 1/15 - - 5
'DDOZ MN = VDD - 0.2V, IOUT = 0 mA VDD = min - - 35
Other Inputs = VDD - 0.2 wo.2v 3.3V i 0.3V Tcycle 1,15 - -
bios, E = VlH or CE2 = I/w. - - 2 mA
0 -85, -10 - 1
Voo = Ta = 25 C -85L, -10L - 0.5 0.7
3V i 10% -85, -10 - - 20
Ta=0°to 70°C -85L,-10L - - 15
o -85, -10 - 2 3
7 bbo = Ta = 25 C -85L, -10L - 0.7 0.9
IDD$2 Standby Current CEI =VDD - 0.2V 3.3v:o.3v -85,-10 - - 25
(Note) or CE2=0.2V Ta=0° to 70°C -85L,-10L - - 20 pr/k
VDD-- 2.0 to 3.6V -85, -10 - - 1
Ta = 25''C -85L, -10L - - 0.5
VDD = 3V o D -85, -10 - - 3
Ta=0 to40''C -85L,-10L - - 2
-85, -10 - - 15
Ta=0°to 70°C -85L,-10L - - 10
Note: In standby mode with m 2 VDD - 0.2 V, these limits are assured for the condition CE2 i VDD - 0.2 V or CE2 s 0.2 V.
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
G: Input Capacitance " = GND 10 F
CouT Output Capacitance VOUT = GND 10 p
Note: This parameter is periodically sampled and is not 100% tested.
1998-03-17 3/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 2.7 to 3.6 V)
READ CYCLE
TC55V1001AF/AFT/ATR/AST/ASR
SYMBOL PARAMETER -85, -85L -10, -10L UNIT
MIN MAX MIN MAX
tRC Read Cycle Time 85 - 100 -
tACC Address Access Time - 85 - 100
tco1 Chip Enable (m) Access Time - 85 - 100
tco2 Chip Enable (CE2) Access Time - 85 - 100
tOE Output Enable Access Time - 45 - 50
tcos Chip Enable Low to Output Active 10 - 10 - ns
tOEE Output Enable Low to Output Active 5 - 5 -
too Chip Enable High to Output High-Z - 30 - 35
tooo Output Enable High to Output High-Z - 30 - 35
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55V1001AF/AFT/ATR/AST/ASR
SYMBOL PARAMETER -85, -85L -10, -10L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 60 - 60 -
tcw Chip Enable to End of Write 75 - 80 -
tAs Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
toow R/W Low to Output High-Z - 30 - 35
tOEw R/W High to Output Active 5 - 5 -
tDS Data Setup Time 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.6 V, 2.2 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, tF: 5 ns
1998-03-17 4/13
TOSHIBA
TIMING DIAGRAMS
TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
READCYcI-E(SeeNote1)
ADDRESS X X
_ tacc t0H
CE2 // tcos "N. "K,
"'% tco1
tOE too
E 'N, //
toss tooo
DOUT t VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
tum tWR
/ tcw W
fig w 7
A tODW tOEW
(See Note 2) (See Note 3)
tos tDH
/(See Note 5) VALID DATA IN (See Note 5)
/h,v,"j2',Di'ir'',',i',',, /
1998-03-17 5/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
WRITE CYCLE 2 LLCEI CONTROLLED) (See Note 4)
ADDRESS X
twe tum
CE2 , tcw 'W"
tcos t00w
tos tDH
De: (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED) (See N ote 4)
ADDRESS
tos tDH
DIN (See Note 5) VALID DATA IN (See Note 5)
1998-03-17 6/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CEI goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If CEI goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 3.6 V
-85, -10 - - 3
Ta = ty' to 40°C
-85L, -10L - - 2
VDH = 3.0V
I s db c T 0°t 70°C -85,-10 - - 15 A
tan rrent a = 0
DDS2 y u -85L,-10L - - IO /2
-85, -10 - - 25
VDH = 3.6V Ta = ty' to 70°C
-85L, -10L - - 20
ttrm Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
CEI CONTROLLED DATA RETENTION MODE (See Note 1)
VDD l DATA RETENTION MODE
2.7 V - - - - - ----_
(See Note 2) (See Note 2)
Ihr, --- l /
- / VDD - 0.2V
CE1 tCDR tR
1998-03-17 7/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
CE2 CONTROLLED DATA RETENTION MODE (See Note 3)
VDD CC") DATA RETENTION MODE hi,
2.7 v ---------'..------------------------i.---------
" tCDR tR
V - - - -
IL k , 0.2 v V
Note: (1) In (El controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V or CE2 2 VDD - 0.2 V.
(2) When CE1 is operating at the Vm level (2 V), the operating current is given by IDDSl
during the transition of VDD from 3.6 to 2.2 V.
(3) In CE2 controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V.
1998-03-17 8/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
Units in mm
'ii2uscsscrvc1s7----,
10 7+0 2
14.13i0.3
(525mil)
_i1ljliierili)ljrrirlrj)
0.775wp " o.3:o.1
21.1MAX
.4 20.6iO.2 pl,
IIII L, .
2 8MAX
0,15 :%.05
Weight: 1.04 g (typ)
1998-03-17 9/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50)
Units in mm
1E 32 CM.
n: k x
El cu.
TT-T , co
ii-g g e;
18.4h0.2 E 1.0:0.1 0.1 i0.05
A 20.0:02 ci 1.2MAX
Weight: 0.34 g (typ)
1998-03-1 7 10/13
Ttts H I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50A)
Units in mm
flfififififififififififlfiflfi
0.2i0.1
8.2MAX
7 9i0 1
18.4i0.2
20.0i0.2
0.1i0.05
0.2TYP
0.15 $.05
0.5:h0.1
Weight: 0.34 g (typ)
1998-03-17 11/13
TOSHIBA
TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0.50)
Units in mm
1;? 112333323 G 1
C": TIEI 6
III]: Elm]; Y,
cu: ===J. 7.
ar an A if: o C;
CI12 31') Ff g c,
E;- Ee?, f ed 00 ;
DI. K I
Lac :DD
ms: :11: -
CH: :11]
16:11 a 17-0-
1 1181-01 E 1 0+01 ii,0-1--"05
co' 1.2MAX
1 13.4i02 ' x "
Weight: 0.24 g (typ)
0 ”5.3.055
ho--1oo
1998-03-17 12/13
TOSHIBA
TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0.50A)
3213! 1:131 g'
cad 01 +1
cu: gl
(:11: - o‘
1:11: :33 V
CH: CCC1TCI-.---'-'=
cm: 333 A
1:11: :1:
EU: :13
CH: ='ICl
:1]: -rr-t
[:1]: CITED
CI Cary I')
El]: :[13
El]: :ILI
17EECL 11:16...
1181-01 _ t
13.4t0.2
Weight: 0.24 g (typ)
8.4MAX
Units in mm
0.1i0.05
1 .2MAX
1998-03-1 7 13/13

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