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TC558128AJ/15-TC558128AJ-15
131,072-WORD BY 8-BIT CMOS STATIC RAM
TOSHIBA
TC558128N-15,-20
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC558128AJ is a 1,048,576-bit hi
words by 8 bits. Fabricated using CMO I"
o erates from a single 5 V power supply. There are two control inputs. Chip ena le (
Reed static random access memory (SRAM) organized as 131,072
nology and advanced circuit techni
ues to rovide high speed, it
CE}; can be used to place
t e device in a low-power mode, and output enable (Off) provides fast memory access. This device is well suited
to cache memory applications where high-s eed access and high-speed storage are reiguired. All inputs and
outputs are directly TTL compatible. The T 558128AJ is available in a plastic 32-pin
width) for high density surface assembly.
FEATURES
0 Fast access time (the following are maximum values)
TC558128AJ-15: 15 ns
T0558128AJ-20: 20 ns
0 Low- ower dissipation
(the allowing are maximum values)
OJ package (400 mil
0 Sin¥le power supply voltage of 5 V i 10%.
o Ful y static operation
0 All inputs and outputs are TIT, compatible
0 Output buffer control using OE
0 Package:
Cycle Time 15 20 25 30 50 ns SOJ32-P-400-1.27A (Weight: 1.22 g typ)
Operation (max) 170 140 130 120 100 mA
Standby: 1 mA (both devices)
PIN ASSIGNMENT BLOCK DIAGRAM
TC558128AJ A10 m
A3|I tl, LI' m MEMORY
A2L at ve.',: Lu CELL ARRAY
AIL A7 8 u, t8 - VDD
Lot 2 It, 0:3 256x512x8 GND
”ng A4 2 m Cy (1,048,576) I
I/02E E A3
6&3: > I/O1
I/O3L a. P02 F- H-
tu: O I/O3 a n: SENSE AMP 2 n:
WEE ti.: I/04 a w 's 'd
A16L I/O5 u. 0 't
A15E < D < m
A14E I/O6 'a m COLUMN 'a
A13L l/O? Cl DECODER 0
g COLUMN ADDRESS
td I- BUFFER
PIN NAMES P, 5
A0 to A16 Address Inputs U tl AOA/kite/yi/yi'
l/OI to |/08 Data Inputs/Outputs
3 Chip Enable
m Write Enable Input
E Output Enable m
VDD Power (+ 5V) -
GND Ground OE
961001 EBAI
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-16 1/8
TOSHIBA TC558128N-15,-20
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.5 to 7.0 V
" Input Terminal Voltage - 2.0* to 7.0 V
VI/o Input/Output Terminal Voltage - 0.5 * to VDD + 0.5 V
PD Power Dissipation 1.1 W
Tsolder Soldering Temperature (10 s) 260 ''C
Tstrg Storage Temperature - 65 to 150 ''C
Topr Operating Temperature - 10 to 85 T
*: - 3V with a pulse width of 10 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = ty' to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5 V
VlH Input High Voltage 2.2 - VDD + 0.5 V
" Input Low Voltage - 0.5 * - 0.8 V
*: - 3V with a pulse width of 10 ns
DC CHARACTERISTICS (Ta = ty' to 70°C, VDD = 5V , 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current " = 0V to VDD - - i 10 [A
E = v W = v E = v
lLo Output Leakage Current IH or IL or IH - - i 10 pzA
VOUT = 0V to VDD
IOH Output High Current VOH = 2.4V - 4 - - mA
IOL Output Low Current VOL = 0.4V 8 - - mA
tcycle = 15 ns - - 170
- tcycle = 20 ns - - 140
CE = 1ho lout = 0mA
IDDO Operating Current tcycle = 25 ns - - 130 mA
Other Inputs = VIH or VIL tcycle = 30 ns - - 120
tcycle = 50 ns - - 100
brrs1 E = VIH, Other Inputs = " or " - - 30
Standby Current E = Moo - 0.2V mA
I - - 1
DDS? Other Inputs = VDD - 0.2V or 0.2V
1997-06-16 2/8
TOSHIBA TC558128N-15,-20
CAPACITANCE (Ta = 25°C,f = 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
ClN Input Capacitance " = GND 6 pF
CI/o Input/Output Capacitance VI/o = GND 8 pF
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE E CE WE I/OI to I/O8 POWER
Read L L H Output IDDO
Write L x L Input IDDO
Outputs Disable L H H High Impedance IDDO
Standby H x x High Impedance IDDS
M : Don't care
1997-06-16 3/8
TOSHIBA
TC558128N-15,-20
AC CHARACTERISTICS(Ta = 0°to 70°C (Note 1),i/DD = 5V , 10%)
READ CYCLE
TC558128AJ-15 TC558128AJ-20
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 15 - 20 -
tAcc Address Access Time - 15 - 20
tco Chip Enable Access Time - 15 - 20
toe Output Enable Access Time - 8 - 10
tor., Output Data Hold Time from Address Change 5 - 5 - ns
tcos Output Enable Time from Chip Enable 5 - 5 -
toss Output Enable Time from Output Enable 1 - 1 -
tcoD Output Disable Time from Chip Enable - 8 - 8
tooo Output Disable Time from Output Enable - 8 - 8
WRITE CYCLE
TC558128AJ-15 TC558128AJ-20
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
twc Write Cycle Time 15 - 20 -
twp Write Pulse Width 9 - 10 -
tcw Chip Enable to End of Write 12 - 13 -
tAW Address Valid to End of Write 12 - 13 -
tas Address Setup Time 0 - O -
tWR Write Recovery Time 0 - 0 -
tos Data Setup Time 8 - 10 -
tDH Data Hold Time 0 - 0 -
toEw Output Enable Time from Write Enable 1 - 1 -
toow Output Disable Time from Write Enable - 8 - 8
AC TEST CONDITIONS FIG.1
- 5 V - 5 V
Input Pulse Level 3.0V, 0.0V
Input Pulse Rise and Fall Time 3 ns 480 Q 480n
. . I o . IO .
Input timing Measurement 1 5V I pm I pm
Reference Level .
CL = 30 pF 255 n CL = 5 pF 255 n
Output Timing Measurement 1 5V I
Reference Level .
(For tcos, toc, tcom
Output Load Fig. 1 tooo, tOEW and t00w)
1997-06-16 4/8
TOSHIBA TC558128N-15,-20
TIMING DIAGRAMS
READ CYCLE (See Note 2)
ADDRESS
OD (See Note 6)
tODO (See Note 6)
EE (See Note
Dout VALID DATA OUT
tcos (See Note 6)
INDETERMINATE INDETERMINATE
WRITE CYCLE 1 (W CONTROLLED) (See Note 5)
ADDRESS X X
tAs twe ’ tWR
WE k _ i!
tODW (See Note 6) tOEw (See Note 6)
Dout (See Note 3) ' (See Note 4)
INDETERMINATE I tos toc INDETERMINATE
Din X VALID DATA IN X
1997-06-16 5/8
TOSHIBA TC558128N-15,-20
WRITE CYCLE 2 (Cl CONTROLLED) (See Note 5)
ADDRESS X X
tAs tWP tWR
E N \ /
to DW (See Note 6)
tCOE (See Note 6)
Dout 7
INDETERMINATE ‘i,(tD_H,
Din VALID DATA IN
1997-06-16 6/8
TOSHIBA TC558128N-15,-20
Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400
linear feet per minute.
(2)WE remains HIGH for the Read Cycle.
(3) If m goes LOW coincident with or after W goes LOW, the outputs will remain
at high impedance.
(4) If C-E goes HIGH coincident with or before W goes HIGH, the outputs will remain
at high impedance.
(5) If tTIT is HIGH during the write cycle, the outputs will remain at high impedance.
(6) The parameters specified below are measured using the load shown in Fig. 1.
(A) tCOE, tOEE, tOEW Output ...... Enable Time
(B) tCOD, tom), tODW Output ...... Disable Time
(A) (B)
f j 0.2 v
y 0.2 v ,
Dom -o' VALID DATA OUT
0.2 V I - 0.2 v
INDETERMINATE ' INDETERMINAT /
1997-06-16 7/8
Tt9SHiBA TC558128N-15,-20
PACKAGE DIMENSIONS
Plastic SO) (SOJ32-P-400-1.27A)
Unitsin mm
Tlr-lt-lt-tr-lr-Ito)..?..,-?!"""],"""?!""?
Cl .2.
m m. t
m m. 9
L..,luJL-lclclclcdulL...ll-Jcliul-lclulcl - I
l a 1...».
I 2t.38MAX N
20.96MM2
|O.8MIN
3 510 2
98 aw“ .
mg . ESQ...
Weight: 1.22g (typ)
1997-06-1 m 8/8
www.ic-phoenix.com
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