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TC554001FTL-70V |TC554001FTL70VTOSHIBAN/a3590avai524, 288 words x 8 bit static RAM, access time 70ns
TC554001FTL-85V |TC554001FTL85VTOSHIBAN/a3400avai524, 288 words x 8 bit static RAM, access time 85ns


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TC554001FTL-70V-TC554001FTL-85V
524, 288 words x 8 bit static RAM, access time 100ns
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288 WORDS M 8 BIT STATIC RAM
DESCRIPTION
The TC554001FL/FTL is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates
from a single 3.0 to 5.5V power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 10mA/MHz(typ) and minimum cycle time of 70 n_s.It is automatically
placed in low-power mode at (Si) PA standby current (max) when chip enable (CE) is asserted high.
There atg_two control inputs. CE is used to select the device and for data retention control, and output
enable (OE) provides fast memory access. This device is well suited to various microprocessor system
applications where hi h speed, low power and battery backup are required.The TC554001FL/FTL is
available in a stan ard plastic 32-pin small-outline paclrige(SOP) and 32-pin thin-small-outline
package(TSOP).
FEATURES
0 Low-power dissipation 0 Access Time (maximum)
Operating: 55 mW/MHz (typical) 5V t 10% 3.0 to 5.5V
0 r?‘taridgyoéllrrel’lt of 8/1A (maxmum) at -70V -851/ -10V -70 V/85 w-lov
0 'lians=n 50w r ll 1 volta of 3 0 to 5 5V Access Time 70 ns 85 ns 100 ns 150 ns
0 Povge: 50w: fzaffrg’s (1tilirel-i1ri . . E Access Time 70 ns 85 m 100 m 150 ns
0 Data retention supply voltage of 2.0 to 5.5V OE Access Time 35 ns 45 ns 50 ns 75 ns
0 Direct TTL compatibility for all inputs and 0 Package:
outputs SOP32-P-525-1.27 (FL) (Weight: 1.14g typ)
TSOPII32-P-400-1.27 (FTL) (Weight: 0.51 g typ)
PIN ASSIGNMENT (TOP VIEW) BLOCK DIAGRAM
O32 PIN FL/FTL CE
A18E1 V 32Cl VDD : v
A161: 2 31] A15 AA18 V, m w --o DD
A14 30] A17 A11 'd,' $1: Sm -oGND
IIC, 29Cl MN A12 m: .1: mm MEMORYCELL
A13 Cy LI. 0 m Cy CI ARRAY
A755 2821A13 A14 24 fall' 28
A15 D 0 LU 1024x512x8
A6 I: 6 27:1 A8 A16 irrn B LU 3 n (4194304)
A5E7 26Cl A9 A17 f?, g“ f,',
A4 E a 25Cl Ag A18
A3 E 9 24Cl OE l/OI
A2 I: 10 23:1 Aio SENSE AMP
A1 E 11 2221 CE el COLUMN ADDRESS
A0 I: 12 21 Cl l/O8 t Eff m
MON: 13 20:1 I/O? o a o
I/O2C 14 19Cl l/O6 08 gg COLUMN ADDRESS
I/O3 E 15 18 Cl I/O5 I/O8 d;
GNDE 16 173 I/O4 tl COLUMN ADDRESS
PIN NAMES
A0 to A18 Address Inputs AOAIA2A3A4A5A6A7A8
R/W Read/Write Control
tN Output Enable
E Chip Enable tN
I/OI to l/O8 Data Input/Output R/W
VDD Power
GND Ground E CE
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-05-18 1/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
OPERATION MODE
OPERATION MODE E E R/W I/OI to I/O8 POWER
Read L L H DOUT IDDO
Write L x L DIN IDDO
Output Disabled L H H High-Z IDDO
Standby H x x High-Z IDDS
Note: M = don't care. H=logic high. L=logic low.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - 0.3* to 7.0 V
Vl/O Input and Output Voltage - 0.5 to VDD + 0.5 V
Po Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 °C
Tstrg. Storage Temperature - 55 to 150 "C
Topr. Operating Temperature 0 to 70 "C
* - 3.0V when measured at a pulse width of 50 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER 5V , 10% 3.0 to 5.5 UNIT
MIN TYP MAX MIN TYP MAX
VDD Power Supply Voltage 4.5 5.0 5.5 3.0 5.0 5.5 V
" Input High Voltage 2.2 - VDD + 0.3 Yoo - 0.2 - VDD + 0.3 V
VlL Input Low Voltage - 0.3* - 0.8 - 0.3* - 0.2 V
VDH Data Retention Supply Voltage 2.0 - 5.5 2.0 - 5.5 V
* - 3.0V when measured at a pulse width of 50 ns
1998-05-18 2/10
TOSHIBA
TC554001FL/FTL-70V,-85V,-10V
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = SV i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
u. Input Leakage Current VIN = 0V to VDD - - i 1.0 PA
C-E = V o-E = V = V
ILO Output Leakage Current C IH or O IH or R/W IL - - , 1.0 szA
VOUT = 0V to VDD
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
E = " and R/W = " min - - 80
'0001 Iour = 0 mA Tcycle mA
Other Inputs = VIHNlL Ire; - 15 -
Operating Current E = 0.2 V and W = l/oo-ORN/ min - - 70
IDDOZ IOUT = 0 mA Tcycle mA
Other Inputs = 1/DD-0.2 V/0.2V Ips - 10 -
|DDS1 tW = " - - mA
VDD = 2.0 to Ta = 25°C - 4 8
5.5V T = 0 t 7 "C - -
Standby Current a 0 o 0 60
Ioosz T = VDD-tMV Ta = 25°C - 2 - PA
VDD = 3.0V Ta = 0 to 40°C - - 6
Ta = 0° to 70°C - - 30
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 3.3V i 0.3V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current " = 0V to VDD - - i 1.0 PA
E = V T = V = V
ILO Output Leakage Current IH or O IH or R/W IL - - i 1.0 ,A
VOUT = 0V to VDD
IOH Output High Current VOH = VDD-0.2V - 0.1 - - mA
IOL Output Low Current VOL = 0.2V 0.1 - - mA
E = 0.2V and R/W = VDD-MV min - _ 35
IDDOZ Operating Current IOUT = 0 mA Tcycle mA
Other Inputs = l/DD-od V/0.2V 1 M; - 5 -
VDD = Ta = 25°C - 2 4
3.3 , 0.3V Ta = (Y' to 70°C - - 40
bose Standby Current E = VoD-0.2 V Ta = 25°C - 2 - pzA
VDD = 3.3V Ta = 0 to 40''C - - 8
Ta = (Y' to 70°C - - 35
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
1998-05-18 3/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 5V , 10%)
READ CYCLE
TC554001FL/FTL
SYMBOL PARAMETER -70V -85V -10V UNIT
MIN MAX MIN MAX MIN MAX
tRC Read Cycle Time 70 - 85 - 100 -
tACC Address Access Time - 70 - 85 - 100
tco Chip Enable Accses Time - 70 - 85 - 100
tog Output Enable Accses Time - 35 - 45 - 50
tcos Chip Enable Low to Output Active 10 - 10 - 10 - ns
toga Output Enable Low to Output Active 5 - 5 - 5 -
too Chip Enable Hige to Output High-Z - 25 - 30 - 35
tODo Output Enable Hige to Output High-Z - 25 - 30 - 35
tom Output Data Hold Time 10 - 10 - 10 -
WRITE CYCLE
TC554001FL/FTL
SYMBOL PARAMETER -70V -85V -10V UNIT
MIN MAX MIN MAX MIN MAX
twc Write Cycle Time 70 - 85 - 100 -
twp Write Pulse Width 50 - 55 - 60 -
tcw Chip Enable to End of Write 60 - 70 - 80 -
tas Address Setup Time 0 - O - 0 -
tWR Write Recovery Time 0 - 0 - 0 - ns
toow MN Low to Output High-Z - 25 - 25 - 25
toew R/W High to Output Active 5 - 5 - 5 -
tos Data Setup Time 30 - 35 - 4O -
tDH Data Hold Time 0 - 0 - 0 -
AC TEST CONDITIONS
Output Load: 30 pF + one TTL gate (-70 V)
100 pF + one TTL gate (-85 V, -10 V)
Input Pulse Level: 0.6V, 2.4V
Timing Measurements: 1.5 V
Reference Level: 1.5 V
tr, ty: 5 ns
1998-05-18 4/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = 0° to 70°C, VDD = 3.0V to 5.5V)
READ CYCLE
SYMBOL PARAMETER MIN MAX UNIT
tRc Read Cycle Time 150 -
tacc Address Access Time - 150
tco Chip Enable (CE) Access Time - 150
toe Output Enable to Output in Valid - 75
tcoE Chip Enable (CE) to Outputin Low-Z 10 - ns
tOEE Output Enable to Output in Low-Z 5 -
too Chip Enable (CE) to Output in High-Z - 50
tODO Output Enable to Output in High-Z - 50
tOH Output Data Hold Time 10 -
WRITE CYCLE
SYMBOL PARAMETER MIN MAX UNIT
twc Write Cycle Time 150 -
twp Write Pulse Width 100 -
tcw Chip Enable to End of Write 120 -
tAs Address Setup Time 0 -
tum Write Recovery Time 0 - ns
toow R/W Low to Output High-Z - 50
tOEW R/W Hige to Output Active 5 -
tDs Data SetupTime 60 -
tDH Data Hold Time 0 -
AC TEST CONDITIONS
Output Load: 100 pF (Include Jig)
Input Pulse Level: VDD - 0.2 V/O.2 V
Timing Measurements: 1.5 V
Reference Level: 1.5 V
tr, tf .' 5 ns
1998-05-18 5/10
TOSHIBA
TIMING WAVEFORMS
READ CYCLE (See Note 1)
ADDRESSES
TC554001FL/FTL-70V,-85V,-1OV
tacc tOH
tOEE tODO
OUTPUT DATA VALID
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESSES
tAS twp tum
f" Ah /
toow toEw
(See Note 2) (See Note 3)
tos tDH
(See Note 5)
DATA IN STABLE
(See Note 5)
1998-05-18 6/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
WRITE CYCLE 2 Lff2Tif CONTROLLED) (See Note 4)
ADDRESSES
tDs tDH
DIN See Note 5 DATA IN STABLE (See Note 5
(1) WW remains High for Read Cycle.
(2) If CE goes coincident with or after R/W goes LOW, the output will remain at high impedance.
(3) If "tTri)"" goes HIGH coincident with or before R/W goes HIGH, the output will remain at high
impedance.
(4) IF CT is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse polarity
must not be applied.
1998-05-18 7/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
l/OH = 3.3V - - 35*
bose Standby Current pA
VDH = 5.5V - - 60
tCDR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
*) 8pA (max) Ta = O" to 40''C
CE Controlled Data Retention Mode
VDD l DATA RETENTION MODE
4.5 V ------ - - - - ------------------.--------- -
(See Note) (See Note)
" --- \ /
- VDD-0.2 V
CE tCDR tR _
Note: When CE is operating at the Vm level (2.2V), the standby current is given by IDDSI
during the transition of VDD from 4.5 to 2.4V.
1998-05-18 8/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
iii2suucsuuvrvc1s7-----a;
10 7i0 2
14.13i0.3
ii1ljlj)ilj)lirielilili11ri,------,
O .775TYP P
h 20.6i0.2 u
2.8MAX
Weight: 1.14 g (typ)
Unit in mm
(525mil)
1998-05-18 9/10
TOSHIBA TC554001FL/FTL-70V,-85V,-1OV
PACKAGE DIMENSIONS (TSOPII 32-P-400-1.27)
Unit in mm
'2RRFlfqRFllqRlqFlFlFlplplpl
1016i01
bfEtihbjbdEEldtildld HHEI
QSSTYP
21 .35MAX
20.95i0.1
1 01—0 1
1.2MAX
0.15 ,0105
Weight: 0.51 g (typ)
1998-05-18 10/10

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