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TC55257CPL-10-TC55257CPL-70-TC55257CPL-85-TC55257CSPL-10-TC55257CSPL-70-TC55257CSPL-85
SILICON GATE CMOS 32,768 WORD x 8 BIT STATIC RAM
T60S)MlllBlh _
T055257CPL/CFL/CspL/CFrL/CrRL-70/85/10
PRELIMINARY
SILICON GATE CMOS
32,768 WORD x 8 BIT STATIC RAM
Description
The TC55257CPL is a 262,144 bit CMOS static random access memory organized as 32,768 words by 8 bits and operated from
a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of
5mA/MHz Exp.) and a minimum cycle time of 70ns. .
When CE is a logical high, the device is placed in a low power_standby mode in which the standby current is 211A at room tem- _
perature. The T055257CEL has two control inputs. Chip enable (CE) allows for device selection and data retention control, while
an output enable input (OE) provides fast memory access. The TC55257CPL is suitable for use in microprocessor systems where
high speed, low power, and battery backup are required.
The TC55257CPL is offered in a standard dual-in-line 28-pin plastic package (0.6/0.3 inch width), a small outline plastic pack-
age, and a thin small outline plastic package (forward type, reverse type).
Features _ Pin Connection (Top View)
. Low power dissipation: 27.5mW/MHZ (15/0) 0 28 PIN DIP & SOP o 28 PIN TSOP
. Standby current: 100PA (max.)
. Single , power supply Am C l . v " , l/oo (forward type) (reverse type)
. Access time (max.) _ m E 2' tr irf,i,' llWiNMlllhil llllillllMllll%
16552576PL/CFL/CSPL/CFTL/CTRL A7 ' " At3 " l . 1 IA
A5 C 4 25 :1 A8
.70 -85 -10 AS C 5 " 3 A9
. A4 C 6 23 3511' _
Access Time 70ns 85ns 100ns A3 C , 22 l OE
CE Access Time 70ns 85ns 100ns A2 t s 21 3 £0
O_EAccess Time 35ns 45ns 50ns AT c, " 5 CE
_ A0 to " 3 1/03
. Power down feature: tTE Ut31 CH 18 gum
. Data retention supply voltage: 2.0 - 5.5V :12: t 1: I; l I',",'
. Inputs and outputs TTL compatible GND t " ts l 1/04
0 Package TC55257CPL 1 DIP28-P-600 " " 28 15
TC55257CFL : SOP28-P-450
T055257QSPL : DF28-P-300B ilflllllllllllllllllllllllll illlllllllllllllllllllllllll
TC55257CFTL : TSOP28-P
TCS5257CTRL 2 TSOP28-P-A
Pin Names
A0 - A14 Address Inputs
RAN Read/Write Control Input
UE outpurEriato Input
CE Chip Enable Input
I/O1 ~ l/O8 Data Input/Output
VDD Power (+5V)
GND Ground
PIN NO. 1 2 3 4 V 5 6 7 8 9 10 11 12 13 14
PIN NAME UE A11 A9 A8 A13 R/IN VDD A14 A12 A7 As As A4 A3
PIN NO. 15 16 17 18 19 20 21 22 _ 23 24 25 26 27 28
PIN NAME A2 N A0 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 IIOS CE Au)
TOSHIBA AMERICA ELECTRONIC COMPONENTS, IND. A-51
III 0007915 i30i?iai?i3Cl E106 D
TC55257CPL/CFL/CSPL/CFTL/tyrRL-70/85/10 Static RAM
Block Diagram
----o VIM)~
A5 m m
A6 a: w ----o GND
A7 tl , t; 5 MEMORY CELL
‘23 8 I' 8 (i) ARRAY
til C?, Ci', 512x64x8
A13 t tk ito (262144)
-..- 54 .....-
1/01 SENSEAMP.
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
REGISTER
DATA CONTROL
GENERATOR
AOA1 A2 A3 A4A10
Operating Mode
PIN EE "t''rE n/w l/01 .. l/08 POWER
MODE '
Read L L H Dem boo
Write . L I L DIN IDDO
Output Deselect L H H High-Z boo
Standby H _ * High-Z IDDS
* H or L
Maximum Ratings
SYMBOL ITEM RATING UNIT
VDD Power Supply Voltage -0.3 ~ 7.0 V
V,” Input Voltage -0.3* ~ 7.0 (
V110 Input and Output Voltage ' -0.5* ~ VDD + 0.5 V
Pro Power Dissipation 1.0/0.8/0.6"* W
TSOLDER Soldering Temperature q Time 260 . 10 'l) . sec
TSTRG Storage Temperature -55 _ 150 _ °C
TOPR Operating Temperature 0 ~ 70 ''C
gr -3.0V with a pulse width of SOns
" Package dependent: 0.6 inch 1.0W. 0.3 inch 0.8W, 0.45 inch 0.6W .
A-52 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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PRELIMINARY
Static RAM TC55257CPL/CFL/CSPL/CFI'L/CTRL-70/85/10
DC Recommended Operating Conditions
SYMBOL PARAMETER MIN. TYP. MAX. UNIT-
VDD Power Supply Voltage 4.5 5.0 5.5
VIH Input High Voltage 2.2 - Voo + 0.3 V
Vic Input Low Voltage -0,3" _ 0.8
VDH Data Retention Supply Voltage _ 2.0 - _ 5.5
' -3.0v with a pylse width of 50ns
DC Characteristics (Ta = 0 - 70°C, VDD = titettPa
SYMBOL PABAMEIEH TEST CONDITION MIN. TYP. MAX. UNIT
L Input Leakage Current _ " = 1) Pe l/oo - - i1.0 PA
'Lo Output Leakage Current SE = V's Srj/W = " or _ = w, - - $1.0 WA
OUT = DD
IOH Output High Current VOH = 2.4V 4.0 - - mA
Ioi. OutpUt Low Current VOL = 0.4V 4.0 - - mA
I CE = VIL tcycle = Ips - 10 -
I R/W = " .
0001 Other Input = VIHNIL twee = Min. cycle - -- 70
IOUT = 0mA _
Operating Current CE = 0.2V tome = Ips - 5 _ mA
R/W = VDD - 0.2V
19002 Other Input . .
= vDD - 0.2V/0.2V tcycle = Min. cycle - - 60
IOUT = 0mA
IL>Ds1 CE = Ihr, - - 3 mA
I Standby Current CE = VDD - 0.2V _ Ta = 0 ~ 70°C _ - 100 WA
DDS? VOD = 2.0V ~ 5.5V Ta = 25°C _ 2 _
. Capabitance” (Ta = 25''C, f = 1MHz)
_ SYMBOL PARAMETER TEST CONDITION MAX. UNIT
Cm Input Capacitance _ VIN = GND 10 F
Cour Output Capacitance VouT = GND 10 p
'This parameter is periodically sampled and is not 100% tested.
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PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-53
TC55257CPL/CFL/CSPL/CFI'L/CTRL-70/85/10 7 Static RAM
AC Characteristics (Ta = 0 ~ 70°C, VDD = 5Vi10%)
Read Cycle T L
T655257CPL/CFL/CSPL/CFTL/CTRI.
SYMBOL PARAMETER -70 .85 . -10 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
inc Read Cycle Time 70 - 85 _ - 100 - .
tacc Address Access Time - 70 -. 85 - 1 00
too JE Access Time . - 70 I T - 85 T 100
tOE Output Enable to Output in Valid - 35 - 45 - 50
1005 Chip Enable (CE) to Output in Low: . 10 - 1' 0 - IO - ns
tOEE Output Enable to Output in Low-Z . 5 - . 5 - 5 -
too Chip Enable (OE) to Output in High-Z . _- 25 - 30 - 50
ttwo Output Enable to Output in High-Z T"' _ 25 - 30 - 40
tOH Output Data Hold Time 10 . - 10 _ 1O -
Write Cycle
[ T055257CPLICFL/CSPL/GFTL/CTHL
SYMBOL PARAMETER -70 -85 -10 _ UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
two Write Cycle Time 70 -' _ 85 - 100 -
twp Write Pulse Width 50 _ 60 - 70 -
Tow Chip Selection to End of Write 60 _ 65 - 90 -
tAS Address Setup Time _ ' 0 - 0' - O -
1WR Write Recovery Time 0 .....' O - 0 - ns
toow RM to Output in High-Z - 25 - 30 - 50
toew RAM to Output in Low-Z T _ 5 - 5 - 5 -
tos Data Setup Time 30 _ - 40 " 40 -
tDH Data Hold Time 0 - 0 - 0 -
AC Test Conditions
Input Pulse Levels 2.4V/0.6V '
Input Pulse. Rise and Fall Time 5ns
Input Timing Measurement Reference Levels 1.5V
Output Timing Measurement Reference Levels 1.5V
Output Load _ 1 TTL Gate and th. = 100pF
'3lyT?i?ttll 0020203 BT'? ©
A-54 TDBHIBA AMERICA ELECTRONIC COMPONENTS, mc. PRELIMINARY
Static RAM TC55257CPL/CFL/CSPL/CFTL/CTRL-70/tpi/1o
Timing Waveforms
Read Cycle tll
ADDRESSES
. Dom OUTPUT DATA VALID
UNKNOWN
Write Cycle 1 (4) (R/W Controlled Write)
twc I F
ADDRESSES
- tos ton
Om DATA STABLE
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PRELIMINARY TDEHIBA AMERICA ELECTRONIC COMPONENTS, IND. _ A-55
TC55257CPL/CFL/CSPL/CFTL/CTFIL-70/85/1 0 Static RAM
Write Cycle 2 (4) (E Controlled Write) .
ADDRESSES'
tos tDH
thr: DATA STABLE
Notes:
I, R/IN is high for read cycles.
2. If the E low transition occurs coincident with or after the R/W low transition, outputs remain in a high impedance
state. .
3. If the tTE high transition occurs coincident with or prior to theR/W high transition, outputs remain
_ in a high impedance state. '
4. If E is high during a write cycle, the outputs are in a high impedance state during this period.
T 5. The l/O may be in the output state,during this time; therefore input signals of opposite phase must not be applied,
D “10517346 0021:1205 17'f cn
A-56 F TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC. PRELIMINARY.
Static RAM TC55257CPL/CFL/CSPL/CFTL/CTRL-70/85/10
Data Retention Characteristics (Ta = 0 - 70°C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
Istz Standby Current VDH = 3.0V - - 50 M
. _ F V VDH = 5.5V - - 1 00
tom Chip Deselect to Data Retention Mode T 0 - _ , T ns
tn Recovery Time _ 190(1) - -
Note (1): Read Cycle Time
FE Controlled Data Retention Mode
l/oo DATA RETENTION MODE
voo-ozv
Note (2): If the vs, of a is 2.2V in operation, bos1 current flows during the period that the VDD voltage is going down from 4.5V to 2.4V.
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PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS. Inc. A-57
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