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TC551664AJ-15-TC551664AJ-20
65,536-WORD BY 16-BIT CMOS STATIC RAM
TOSHIBA TC551664N-15,-20
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
65,536-WORD BY16-BIT CMOS STATIC RAM
DESCRI PTIO N
The TC551664AJ is a 1,048,576-bit high-speed static random access memory (SRAM) organized as 65,536
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 5 V power supply. Chip enable (UE) can be used to place the device in a low-power mode,
and output enable (OT) provides fast memory access. Data byte control signals (E, W) provide lower and
upper byte access. This device is well suited to cache memory applications where high-speed access and high-
speed storage are required. All inputs and outputs are directly TTL compatible. The TC551664AJ is available
in a plastic 44-pin SOJ package (400 mil width) for high density surface assembly.
F EAT U R ES
0 Fast access time (the following are maximum values) 0 Single power supply voltage of 5 V i 10%.
TC551664AJ-15: 15 ns 0 Fully static operation
TC551664AJ-20: 20 ns 0 All inputs and outputs are TTL compatible
0 Low-power dissipation Output buffer control usi_n_g 6E _...............
(the following are maximum values) Data byte control using LB (101 to 108) and UB
Cycle Time 15 20 25 30 50 ns (109 to 1016)
Operation (max) 260 220 200 180 150 mA er Package: .
Standby: 1mA(bothdevices) SOJ44-P-400-1.27(We1ght:1.64gtyp)
PIN ASSIGNMENT PIN NAMES
TC551664AJ A0 to A15 Address Inputs
A4 L 1 44 ZIAS IIO1 t:|/O16 Data Inputs/Outputs
A3 E 2 43 II A6 CE Chip Enable
12 f , 2: 3% W Write Enable Input
A0 L 5 40 JW _OE_ Output Enable
E E 6 39 il E LB, UB Data Byte Control Input
IIO1 L 7 A 38 J l/O16 Yoo Power (+ 5V)
IIOZ E 8 E 37 J IIO15
1/03 L 9 Lu 36 1 1/014 GND Ground
I/O4 E 10 , 35 Cl IIO13 NC No Connection
VDD I: 11 34 1 GND
GNDE 12 o. 33 l l/DD NU Not Used (Input)
|/05 13 C) 32 211/012
I/06E 14 t 31 31/011
l/O? L 15 30 31/010
|/O_8 E 16 29 l l/O9
WE E 17 28 II NU
A15 E 18 27 1 A8
A14 E 19 26 II A9
A13 C 20 25 :1 A10
A12 C 21 24 2 A11
NC E 22 23 3 NC
961001 EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-16 1/8
TOSHIBA
BLOCK DIAG RAM
BUFFER
ADDRESS
5 FFER
DECODER
GENERATOR
n r— C 0‘
MAXIMUM RATINGS
TC551664N-15,-20
MEMORY
CELL ARRAY
256 X 256 X 16
(1,048,576)
OUTPUT
BUFF ER
SENSE AMP
OUTPUT
COLUMN
DECODER
BUFFER
COLUMN
ADDRESS BUFFER
A0 A2 A12 A14
A1 A11A13 A15
SYMBOL RATING VALUE UNIT
Yoo Power Supply Voltage - 0.5 to 7.0 V
" Input Terminal Voltage - 2.0 * to 7.0 V
VI/o Input/Output Terminal Voltage - 0.5 * to VDD + 0.5 V
Po Power Dissipation 1.5 W
Tsolder Soldering Temperature (10 s) 260 T
Tstrg Storage Temperature - 65 to 150 ''C
Topr Operating Temperature - 10 to 85 T
tir.' - 3V with a pulse width of 10 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5 V
" Input High Voltage 2.2 - VDD + 0.5 V
" Input Low Voltage - 0.5 * - 0.8 V
*: - 3V with a pulse width of 10 ns
1997-06-16 2/8
TOSHIBA TC551664N-15,-20
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 5V i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
I Input Leakage Current V 0V t V + 10
IL (Except NU Pin) IN - 0 DD - - FA
c7 = V W = V o-E = V
ILo Output Leakage Current C IH or IL or O IH - - + 10 #A
VOUT = 0V to VDD
I Input Current V 0 t 0 8V 1 20
I(NU) (NU Pin) IN - o _ - - #A
IOH Output High Current VOH = 2.4V - 4 - - mA
IOL Output Low Current VOL = 0.4V 8 - - mA
tcycle = 15 ns - - 260
- tcycle = 20 ns - - 220
E = Ihr, Iout = 0mA
IDDO Operating Current tcycle = 25 ns - - 200 mA
Other Inputs = VIH or VIL tcycle = 30 ns _ - 180
tcycle = 50 ns - - 150
bor E = VIH: Other Inputs = " or " - - 30
I Standby Current E = VDD - 0.2V 1 mA
DDS? Other Inputs = VDD - 0.2V or 0.2V
CAPACITANCE (Ta = 25°C,f = 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
Cm: Input Capacitance " = GND 6 pF
CI/o Input/Output Capacitance Vvo = GND 8 pF
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE E E WE cg W I/O1 to I/O8 [/09 to I/OIF POWER
L L Output Output boo
Read L L H H L High Impedance Output boo
L H Output High Impedance boo
L L Input Input IDDO
Write L x L H L High Impedance Input IDDO
L H Input High Impedance boo
L H H x x
Outputs Disable High Impedance High Impedance IDDO
L x x H H
Standby H x x x x High Impedance High Impedance [DDS
X : Don't care
Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8V to the NU.
1997-06-16 3/8
TOSHIBA
TC551664N-15,-20
AC CHARACTERISTICS(Ta = ty' to 70°C (Note 1), VDD = 5V i 10%)
READ CYCLE
TC551664AJ-15 TC551664AJ-20
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 15 - 20 -
tAcc Address Access Time - 15 - 20
tco Chip Enable Access Time - 15 - 20
tog Output Enable Access Time - 8 - IO
tBA Upper Byte, Lower Byte Access Time - 8 - 10
to... Output Data Hold Time from Address Change 5 - 5 -
tCOE Output Enable Time from Chip Enable 5 - 5 -
toss Output Enable Time from Output Enable 1 - 1 -
tBE Output Enable Time from Upper Byte, Lower Byte 1 - 1 -
tcoD Output Disable Time from Chip Enable - 8 - 8
tooo Output Disable Time from Output Enable - 8 - 8
tBD Output Disable Time from Upper Byte, Lower Byte - 8 - 8
WRITE CYCLE
TC551664AJ-15 TC551664AJ-20
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
twc Write Cycle Time 15 - 20 -
twp Write Pulse Width 9 - 10 -
tcw Chip Enable to End of Write 12 - 13 -
th Upper Byte, Lower Byte Enable to End of Write 12 - 12 -
taw Address Valid to End of Write 12 - 12 -
tas Address Setup Time 0 - 0 - ns
tWR Write Recovery Time 0 - O -
tog Data Setup Time 8 - 10 -
tDH Data Hold Time 0 - 0 -
tOEW Output Enable Time from Write Enable 1 - 1 -
toow Output Disable Time from Write Enable - 8 - 8
AC TEST CONDITIONS FIG.1
5 V 5 V
Input Pulse Level 3.0V, 0.0V
Input Pulse Rise and Fall Time 3 ns 480 Q 480Q
" pin " pin
Input Timing Measurement 1 5V
Reference Level CL = 30 pF 255 n CL = 5 pF 255 n
Output Timing Measurement 1 5V
Reference Level .
(For tcos, toss, tBE, tcoo,
Output Load Fig. 1 tooo, tBD, tow and toow)
1997-06-16 4/8
TOSHIBA TC551664N-15,-20
TIMING DIAGRAMS
ADDRESS
tCOD (See Note 6)
tooo (See Note 6)
tBE (See Note 6)
t (See Note 6)
Note 6 BD
Dout VALID DATA OUT
tCOE (See Note 6)
INDETERMINATE INDETERMINATE
WRITE CYCLE 1 (W CONTROLLED) (See Note 5)
ADDRESS X X
tAs twe ’ tWR
WE k _ i!
E A, 2/
UB, LIT _ ii
toow (See Note 6) tOEW (See Note 6)
'25 (See Note 4)
INDETERMINATE I tDS toc INDETERMINATE
Din )k VALID DATA IN X
1997-06-16 5/8
TOSHIBA TC551664N-15,-20
WRITE CYCLE 2 (Cl CONTROLLED) (See Note 5)
ADDRESS X X
tAs twe tWR
m 'Rs, /'"
- S , l
E tie, \ ,
w, m "N /
tBE (See Note 6)
tODW (See Note 6)
t (See Note G)
Dout COE 9
INDETERMINATE etc-rs-tr-sri,
Din VALID DATA IN
WRITE CYCLE 3 (W, LIT CONTROLLED) (See Note 5)
ADDRESS X X
tAs twp tWR
WE \ 2%
CE _ i
tBE (See Note 6)
toow (Seel Note 6)
tCOE (See Note 6)
INDETERMINATE I tos _ tDH -
Din VALID DATA IN
1997-06-16 6/8
TOSHIBA TC551664N-15,-20
Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400
linear feet per minute.
(2)WE remains HIGH for the Read Cycle.
(3) If m goes LOW coincident with or after W goes LOW, the outputs will remain
at high impedance.
(4) If C-E goes HIGH coincident with or before W goes HIGH, the outputs will remain
at high impedance.
(5) If tTIT is HIGH during the write cycle, the outputs will remain at high impedance.
(6) The parameters specified below are measured using the load shown in Fig. 1.
(A) tCOE, tOEE, tBE, tOEW ...... Output Enable Time
(B) tCOD, toDo, tBD, tonw ...... Output Disable Time
(A) (B)
l j 0.2 v
y 0.2 v ,
-o' VALID DATA OUT
0.2 V e - 0.2 v
INDETERMINATE ' INDETERMINATE /
1997-06-16 7/8
TOSHIBA TC551664N-15,-20
PACKAGE DIMENSIONS
Plastic SO) (Soj44-P-400-1.27)
Unitsinmm
(''-ll-lrlf-lrnf-lrTr'-lrli-lr1f-'iri_r-1rir-nr-irIi-qr1r1
53. g a
'i'iiii' s
". c? 0)
b-ll-lL-dl-jr-ll-JI-lL-ll-ji-lt-dt-JI-jr-lL-jr-It-IL-it-ir-dt-it-l
29.0MAX
28.58i0.12
Weight: 1.64 g (typ)
1997-06-16 8/8
www.ic-phoenix.com
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