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TC551001CFI70LTOSHIBAN/a240avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFI-70L |TC551001CFI70LTOSHIBAN/a2000avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFI-85 |TC551001CFI85TOSHIBAN/a3000avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFI-85L |TC551001CFI85LTOSHN/a200avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFTI-70 |TC551001CFTI70TOSHIBAN/a3600avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFTI-70L |TC551001CFTI70LTOSHIBAN/a8000avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFTI-70L |TC551001CFTI70LTOSHN/a294avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFTI-85 |TC551001CFTI85TOSHIBAN/a3596avai131,072 WORD x 8 BIT STATIC RAM
TC551001CFTI-85L |TC551001CFTI85LTOSHIBAN/a3956avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-70 |TC551001CPI70TOSHIBAN/a5380avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-70L |TC551001CPI70LTOSHIBAN/a5704avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-70L |TC551001CPI70LTOSHN/a48avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-85 |TC551001CPI85TOSN/a120avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-85L |TC551001CPI85LTOSN/a2avai131,072 WORD x 8 BIT STATIC RAM
TC551001CPI-85L |TC551001CPI85LTOSHIBAN/a6000avai131,072 WORD x 8 BIT STATIC RAM
TC551001CSTI-70L |TC551001CSTI70LTOSHIBA ?N/a30avai131,072 WORD x 8 BIT STATIC RAM
TC551001CSTI-85L |TC551001CSTI85LTOSN/a971avai131,072 WORD x 8 BIT STATIC RAM
TC551001CTRI-70L |TC551001CTRI70LTOSHIBAN/a37459avai131,072 WORD x 8 BIT STATIC RAM


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TC551001CFI70L-TC551001CFI-70L-TC551001CFI-85-TC551001CFI-85L-TC551001CFTI-70-TC551001CFTI-70L-TC551001CFTI-85-TC551001CFTI-85L-TC551001CPI-70-TC551001CPI-70L-TC551001CPI-85-TC551001CPI-85L-TC551001CSTI-70L-TC551001CSTI-85L-TC551001CTRI-70L
131,072 WORD x 8 BIT STATIC RAM
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131 ,072-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC551001CPI/CFI/CFTI/CTRI/CSTI/CSRI is a 1,048,576-bit static random access memory (SRAM)
organized as 131,072 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 5 V i' 10% power supply. Advanced circuit technology provides both high speed
and low power at an operating current of 5 mA/MHz (typ) and a minimum cycle time of 70 ns. It is
automatically placed in low-power mode at 1 PA standby current (typ) when chip enable (CE1) is asserted
high or (CE2) is asserted low. There are threesntrol inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable (OE) provides fast memory access. This device is well suited to
various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of - 40° to 85°C, the TC551001CPI/CFI/CFTI/CTRl/CSTI/CSRI can
be used in environments exhibiting extreme temperature conditions. The TC5510010PI/CFI/CFTI/CTRI/
CSTI/CSRI is available in a standard plastic 32-pin dual-in-line package (DIP), plastic 32-pin small-outline
package (SOP) and normal and reverse pinout plastic 32-pin thin-small-outline package (TSOP).
FEATURES
0 Low-power dissipation 0 Access Times (maximum):
o Si Olperating‘: 27 51 le/tMHz (£130th TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRI
mg e power supp y vo age 0 - o -70, -70L -85, -85L
0 Power down features using CE1 and CE2. Access Time 70 ns 85 ns
0 Data retention supply voltage of 2 to 5.5 V w Access Time 70 ns 85 ns
0 Direct TTL compatibility for all inputs and CE2 A .
outputs - ccess Time 70 ns 85 ns
0 Wide operating temperature range of - 40° to OE Access Time 35 ns 45 ns
85°C 0 Packages:
0 Standby Current(maximum) : DIP32-P-600-2.54 (CPI) (Weight: 4.45 gtyp)
TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl SOP32-P-525-1.27 (CW) (Weight: 1.04 g typ)
-70 -85 -70L -85L TSOPI32-P-0820-0.50(CFTI) (Weight: 0.34 gtyp)
' ' TSOPI32-P-0820-0.50A(CTRI) (Weight:0.34gtyp)
5.5V 200 PA 40 PA TSOP I 32-P-0.50 (CSTI) (Weight: 0.24 g typ)
3.ov 100 PA 20 prA TSOP I 32-P-0.5OA (CSRI) (Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
o 32 PIN DIP & SOP o 32 PIN TSOP
NC I: 1 V 32: V00 (Normalpinout) (Reverse pinout)
A16 l: 2 31 El A15
A14 C 3 30D CE2
A12 1: 4 293 16 1
A7 1: 5 28: A13
A6 I: 6 27:1 A8
A5 I: 7 263 A9
A4 C 8 25:1 w
A3 I: 9 24: OE
A2 I: 10 23:1 m
A1 1: 11 22ZI CE1
A0 C 12 21 El I/O8
1/01 I: 13 20] V07
V02 E 14 rg (fits' 17 32
£83512 17:1 I/O4
PIN NAMES
AOSWNG :ddézzjllspuclts t I PinNo. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
E (1C,/uvl"J,ealf',n ro PinName A11 A9 N A13 R/W CE2 A15 VDD NC A15 A14 A12 A7 As As A4
a, CE2 Chip Enable Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
l/OI to I/O8 Data Input/Output Pin Name N A2 A1 A0 l/OI 1/02 1/03 GND I/04 1/05 I/O6 l/O? I/O8 m A10 o"
VDD Power (+ 5V)
GND Ground
NC No Connection
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-19 1/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
BLOCK DIAGRAM
A4 -o VDD
£2 a a a --o GND
A7 'tl :1: E MEMORY CELL
shul ga, SE fit ARRAY
A13 ft' " if?, 1024x128x8
/hlt 55 tg y? (1048576)
A16 tern ttctts cm
I/OI SENSEAMP
d COLUMNADDRESS
, f/ir, s
m, t COLUMNADDRESS
l/O8 8;
dll) COLUMNADDRESS
A0 A2 9
A1 A? A A10A11
OPERATION MODE
MODE W CE2 E MN I/OI to l/O8 POWER
Read L H L H DOUT IDDO
Write L H X L DIN IDDO
Outputs Disabled L H H H High-Z IDDO
H x x x High-Z IDDS
Standby .
X L X X High-Z IDDS
Note: x = don't care. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - 0.3* to 7.0 V
l/vo Input and Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 1.0/0.6** W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg. Storage Temperature - 55 to 150 T
Topr. Operating Temperature - 40 to 85 "C
* - 3.0 V when measured at a pulse width of 50 ns ** SOP
1997-06-19 2/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5
" Input High Voltage 2.4 - VDD + 0.3 V
I/w. Input Low Voltage - 0.3* - 0.6
VDH Data Retention Supply Voltage 2.0 - 5.5
* - 3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS(Ta = - 40° to 85°C,VDD = 51/ , 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VlN = 0V to VDD - - i 1.0 PA
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 4.0 - - mA
CE1 = " or CE2 = VIL or R/W = " or
ILO Output Leakage Current - - - , 1.0 PA
OE = VIH: VOUT = 0V to VDD
W = " and CE2 = " .
mm - - 70
and MN = VIH:
Ioryol Tcycle mA
IOUT = 0 mA 1 20
. Other Inputs = VIHNlL pd;
Operating Current -
CE1 = 0.2V and CE2 = VDD - 0.2V
min - - 60
MN = VDD - 0.2 v,
'DDOZ Tcycle mA
IOUT = 0 mA 10
Other Inputs = VDD - 0.2 V/0.2V Irs
|DDs1 til = " or CE2 = " - - 3 mA
Ta = 2S'C - 1 -
- -70 -85
E1 = V - .2V I o o
IDDSZ Standby Current C DD 0 Ta=-40 to 85 C - - 200
(Note) or CE2 = 0.2V T 25 C 1 2 ttA
a-- t9 -
VDD = 2.0 to 5.5V -7OL,-85L
Ta = -40'' to 85°C - - 40
Note: In standby mode with m L2 VDD - 0.2 V, these limits are assured for the condition CE2 L2 VDD - 0.2 V or CE2 E 0.2 V.
CAPACITANCE (Ta = 25tf = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 F
COUT Output Capacitance VOUT = GND 10 p
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-19 3/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 5 V i 10%)
READ CYCLE
TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRI
SYMBOL PARAMETER -70, -70L -85, -85L UNIT
MIN MAX MIN MAX
tRC Read Cycle Time 70 - 85 -
tAcc Address Access Time - 7O - 85
tco1 Chip Enable (w) Access Time - 70 - 85
tco2 Chip Enable (CE2) Access Time - 70 - 85
tOE Output Enable Access Time - 35 - 45
tcos Chip Enable Low to Output Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - 0 -
too Chip Enable High to Output High-Z - 30 - 35
tooo Output Enable High to Output High-Z - 30 - 35
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl
SYMBOL PARAMETER -70, -70L -8S, -85L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 70 - 85 -
twp Write Pulse Width 50 - 60 -
tcw Chip Enable to End of Write 60 - 75 -
tAS Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
tODW R/W Low to Output High-Z - 3O - 35
tOEw R/W High to Output Active 0 - 0 -
tDS Data Setup Time 30 - 35 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.6 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, tF: 5 ns
1997-06-19 4/14
TOSHIBA
TIMING DIAGRAMS
TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
READCYcI-E(SeeNote1)
ADDRESS X X
_ tacc t0H
CE2 // tcos "N. "K,
"'% tco1
tOE too
E 'N, //
toss tooo
DOUT t VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
tum tWR
/ tcw W
fig w 7
A tODW tOEW
(See Note 2) (See Note 3)
tos tDH
/(See Note 5) VALID DATA IN (See Note 5)
/h,v,"j2',Di'ir'',',i',',, /
1997-06-19 5/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
WRITE CYCLE 2 LLCEI CONTROLLED) (See Note 4)
ADDRESS X
twe tum
CE2 , tcw 'W"
tcos t00w
tos tDH
De: (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED) (See N ote 4)
ADDRESS
tos tDH
DIN (See Note 5) VALID DATA IN (See Note 5)
1997-06-19 6/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CEI goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If CEI goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
l/DH = 3.0V - - 100
-70, -85
VDH = 5.5V - - 200
IDDSZ Standby Current ,aA
VDH = 3.0V - - 20*
-70L, -85L
VDH = 5.5V - - 40
thR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
* 2;1A(max)at Ta = - 40°to 40°C
CEI CONTROLLED DATA RETENTION MODE (See Note 1)
VDD l DATA RETENTION MODE
4.5 V _-..-..-..-..-..-. - - - - "_.-..-..-..-..-..-..-..-..-..-..-.-.-..-..-..-..-.
(See Note 2) (See Note 2)
Ihr, --- l /
- / VDD - 0.2 V
CE1 ‘ tCDR tR ’
1997-06-19 7/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
CE2 CONTROLLED DATA RETENTION MODE (See Note 3)
VDD CC) DATA RETENTION MODE hi,
4.5 v ---------'..------------------------i.---------
" tCDR tR
V - - - -
IL k , 0.2 v V
Note: (1) In (El controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V or CE2 2 VDD - 0.2 V.
(2) When CEI is operating at the VIH level (2.4 V), the operation current is given by IDDSl
during the transition of VDD from 4.5 to 2.6 V.
(3) In CE2 controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V.
1997-06-19 8/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
PACKAGE DIMENSIONS (DIP32-P-600-2.54)
Units in mm
42.5MAX
42.0i0.2
i? g'.
lf tl Ln. ti
I l l 2. I I E O
U P LO
1.95wp 1.4_0.1 ”0.5_0.1 0.25®
Weight: 4.459 (typ)
1997-06-19 9/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
Units in mm
'ii2uscsscrvc1s7----,
10 7+0 2
14.13i0.3
(525mil)
_i1ljliierili)ljrrirlrj)
0.775wp " o.3:o.1
21.1MAX
.4 20.6iO.2 pl,
IIII L, .
2 8MAX
0,15 :%.05
Weight: 1.04 g (typ)
1997-06-19 10/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50)
Units in mm
1E 32 CM.
n: k x
El cu.
TT-T , co
ii-g g e;
18.4h0.2 E 1.0:0.1 0.1 i0.05
20.0:02 ci 1.2MAX
Weight: 0.34 g (typ)
1997-06-19 11/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50A)
Units in mm
+l A ----
1% 1 cu. c-----:.
CD 11: o
'i:', ' Q g-
E is. tl
'3: / Ln CO ts
iig Cid',]
16 a.'
18.4ur0.2 = E 1.0kihl 0.1 i005
20.0:02 _ ci 1.2MAX
0.5:h0.1
Weight: 0.34 g (typ)
1997-06-19 12/14
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50)
TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
Units in mm
1;? 112333323 G 1
C": TIEI 6
III]: Elm]; Y,
cu: ===J. 7.
ar an A if: o C;
CI12 31') Ff g c,
E;- Ee?, f ed 00 ;
DI. K I
Lac :DD
ms: :11: -
CH: :11]
16:11 a 17-0-
1 1181-01 E 1 0+01 ii,0-1--"05
co' 1.2MAX
1 13.4i02 ' x "
Weight: 0.24 g (typ)
0 ”5.3.055
ho--1oo
1997-06-19 13/14
TOSHIBA TC551001CPl/CFl/CFTl/CTRl/CSTl/CSRl-70,-85,-70L,-85L
PACKAGE DIMENSIONS (TSOP I 32-P-0.50A)
Units in mm
32:11: T2131 ci T
cad CD +1
cu: gl
(:11: - o‘
:11: Elm]; v, I
:13: -
Eu: III] A Q "l _
1:13: :EEI CE
cu: ='ICl - _
ED: -rr-t I
[:1]: CITED
El]: 31:: CD
El]: :ILI
17EECL 11:16...
1181-01 " ,Z 0.110.05
13.4t0.2 " 1.2MAX
Weight: 0.24 g (typ)
1997-06-19 14/14

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