TC528128BJ-80 ,80ns; V(cc): -1 to +7V; V(in/out); -1.0 to +7.0V; 1W; 50mA; silicon gate CMOS 131.072 words x 8 Bits multiport DRAMTOS H I BA TC528128B
SILICON GATE CMOS t a r g e t S p e C
131,072WORDSX8BITS MULTIPORT DRAM
..
TC531001CP ,120ns; V(dd): -0.5 to +7V; 1M bit (128K word x 8 bit) CMOS MASK ROMIll BIT (128K HORD x 8 BIT) CHOS MASK RON
SILICON GATE CHOS
DESCRI PTION
The TC53lOOlCP/CF i ..
TC531024P-15 ,150ns; 5V; 1M bit (65,536 word x 16bit) CMOS MASK ROMFEATURES
TCS31024PIF - 12 - 15 . Single 5V Power Supply
PowerSupply 5V.t5% 5Vf.10% . Fully Stat ..
TC53257P , 256K BIT (32K WORD x 8 BIT) CMOS MASK ROM SILICON GATE MOS
TC53257P , 256K BIT (32K WORD x 8 BIT) CMOS MASK ROM SILICON GATE MOS
TC54256 , 32,768 WORD x 8 BIT CMOS ONE TIME PROGRAMMABLE READ ONLY MEMORY
TC83220-0006 ,Single-Chip CMOS LSI for FL (fluorescent) CalculatorFeatures Print: 12 digits of data. Weight: 4.12 g (typ.) (including decimal point and minus sig ..
TC83220-0009 ,Single-Chip CMOS LSI for FL (fluorescent) Calculator with PrintersTC83220-0009 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC83220-0009 TC83220-000 ..
TC83220-0009 ,Single-Chip CMOS LSI for FL (fluorescent) Calculator with PrintersFeatures Print: 12/14 digits of data. Weight: 4.12 g (typ.) (including decimal point and minus ..
TC83220-0019 ,Single-Chip CMOS LSI for FL (fluorescent) Calculator with PrintersFeatures Print: 11 or 13 digits of data. Weight: 4.12 g (typ.) (including decimal point) 1 digi ..
TC83220-0020 ,Single-Chip CMOS LSI for FL (fluorescent) CalculatorTC83220-0020 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC83220-0020 TC83220-002 ..
TC83220-0021 ,Single-Chip CMOS LSI for FL (fluorescent) CalculatorFeatures Print: 11 or 13 digits of data. (including decimal point. 2 digits of operational symbo ..
TC528128BJ-10-TC528128BJ-80
100ns; V(cc): -1 to +7V; V(in/out); -1.0 to +7.0V; 1W; 50mA; silicon gate CMOS 131.072 words x 8 Bits multiport DRAM
''irC(0S)ly(llr)?hh
SILICON GATE CMOS
TC528128B
target
131,072WORDSX8BITS MULTIPORT DRAM
DESCRIPTION
The TC528128B is a CMOS multiport memory equipped with a l3l,072-words by 8-bits dynamic random
access memory (RAM) port and a 256-words by 8-bits static serial access memory (SAM) port. The TC528128B
supports three types of operations; Random access to and from the RAM port, high speed serial access to and
from the SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM
port. The RAM port and the SAM port can be accessed independently except when data is being transferred
between them internally. In addition to the conventional multiport videoram operating modes, the TC528128B
features the block write and flash write functions on the RAM port and a split register data transfer capability
on the SAM port. The TC528128B is fabricated usin g Toshiba's CMOS silicon gate process as well as advanced
circuit designs to provide low power dissipation and wide operating margins.
FEATURES
. Single power supply of 5Vi10% with a built-in
VBB generator
. All inputs and outputs : TTL Compatible
. Organization
RAM Port : 131,072 wordsX8bits
SAM Port : 256 wordsX8bits
. RAM Port
Fast Page Mode Read - Modify - Write
CTiT; before ITM Refresh, Hidden Refresh
EA-f, only Refresh, Write per Bit
Flash Write, Block Write
512 refresh cycles / 8ms
. SAM Port
High Speed Serial Read / Write Capability 256
Tap Locations
Fully Static Register
. RAM - SAM Bidirectional Transfer
Read / Write / Pseudo Write Transfer
Real Time Read Transfer
Split Read / Write Transfer
. Package
TC52812881 : SOJ40-PM00
TC528128BZ: ZIP40-P-475
KEY PARAMETERS
TC528128B
- 80 - 10
IRAC RAS Access Time 80ns lOOns
(Max.)
tCAC CAS Access Time 25ns 25ns
(Max.)
tAA Celumn Address Access 45ns 50ns
Time (Max.)
tRC Cycle Time (Min.) 150ns 180ns
tec Page Mode Cycle Time SOns 55ns
(Min.)
tSCA Serial Access Time 25ns 25ns
(Max.)
tSCC Serial Cycle Time (Min.) 30ns 30ns
ICCI RAM Operating Current
(SAM : Standby) 90mA 75 mA
SAM Operating Current
(RAM : Standby) 50mA 50mA
I CC2 Standby Current 10mA 10mA
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
PIN NAME
A0-A8 Address inputs
m Row Address Strobe
Ch-g Column Address Strobe
ltr/trt? Data Transfer/Output Enable
WW Write per Bit/Write Enable
DSF Special Function Control
WI/lOl ~W4/IO8 Write Mask/Data IN, OUT
SC Serial Clock
E Serial Enable
SIOl-SIO8 Serial Input/Output
QSF Special Flag Output
Vcc/Vss Power(5V)/Ground
N.C. No Connection
PIN CONNECTION (TOP VIEW)
157/6!
W1 tlOl
W2 t It32
W3 / l03
W4] I04
WEI WE
ONOMbNN
TC528128N
J Vss1
l snoa
J SK)?
J suos
J 5105
l W8/IO8
l W7/IO7
32] wsnos
3t J wsnos
30] V552
29J DSF
28] NC
27 l HS
26] QSF
25 J A0
243 A1
ts? A2
22] A3
21 3 A7
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
BLOCK DIAGRAM
W1/lO1~W8/l08
EB £33
????1??
SERIAL OUTPUT
BUFFER
SERIAL INPUT
BUFFER
OUTPUT BUFFER INPUT BUFFER TIMING GENERATOR
CONTROL
REGISTER
(8bit)
CONTROL
REGISTER
(8bit)
CONTROL
WRITE-PER
TRANSFER
CONTROL
TR. GATE
Selettor
512x256x8
COLUAM DECODER
SENSE AMPLIFIER
Set In
Seiector
05F QSF
SERIAL ADDRESS
COUNTER (8bits)
ROW DECODER
Vcc Vss
COLUMN ADDRESS
BUFFER (8bits)
ROW ADDRESS
BUFFER (9bits)
REFRESH
COUNTER
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-115
TC528128B
ABSOLUTE MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT NOTE
VIN, VOUT Input Output Voltage - LO-7.0 V l
Vcc Power Supply Voltage - LO--'? .0 V l
TOPR Operating Temperature 0-70 ''C 1
TSTG Storage Temperature - 55--150 °C 1
TSOLDER Soldering Temperature . Time 260-10 °C-sec 1
PD Power Dissipation 1 W l
IOUT Short Circuit Output Current 50 mA 1
RECOMMENDED D.C. OPERATING CONDITIONS (Ta = 0~70°C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE
VCC Power Supply Voltage 4 5 5.0 5.5 V 2
Vm Input High Voltage 2.4 - 6.5 V 2
VIL Input Low Voltage -1.0 - 0.8 V 2
CAPACITANCE (Vcc=5V, f=1MHz, Ta=25°C)
SYMBOL PARAMETER MIN. MAX. UNIT
c, Input Capacitance - 7
Cro Input/Output Capacitance - 9 pF
Co Output Capacitance (QSF) - 9
Note: This parameter is periodically sampled and is not 100% tested.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
D.C. ELECTRICAL CHARACTERISTICS (Vcc = 5V i 10%, Ta = 0~70°C)
-80 -10
ITEM (RAM PORT) SAM PORT SYMBOL UNIT NOTE
MIN. MAX. MIN. MAX.
OPERATING CURRENT Standby [cc] - 90 - 75 3, 4
RAS, CAS Cycling
tRC = tRC min. Active [CCIA - 130 - 115 3, 4
STANDBY CURRENT Standby ICC2 - 10 - 10
(RAS, CAS = VIH)
Active ICC2A - 50 - 50 3, 4
RAS ONLY REFRESH CURRENT Standby ICC3 - 90 - 75 3, 4
ms Cycling, CAS = VIH
(C), = tRC min. ) Active ICC3A - I30 - ll5 3, 4
PAGE MODE CURRENT Standby ICC4 - 80 - 65 3, 4
RAS = VIL, CAS Cycling
YC = tRC min. Active ICC“ - no - 105 3, 4
CAS BEFORE RAS REFRESH CURRENT Standby ICC5 - 90 - 75 3, 4
RAS Cycling, CAS Before RAS
tRC =tRC min. Active ICCSA - 130 - 115 3, 4
DATA TRANSFER CURRENT Standby ICC6 - 110 - 95 3, 4
RAS, CAS Cycling
tRC = tRC min. Active ICCM - 150 - 135 3, 4
FLASH WRITE CURRENT Standby 1CC7 - 100 - 75 3. 4
RAS, CAS Cycling
tRC =1RC min. Active ICC7A - I30 - 115 3, 4
BLOCK WRITE CURRENT Standby Iccg - 100 - 85 3, 4
RAS, CAS Cycling
tRC = tec: min. Active ICCSA - l40 w 125 3, 4
ITEM SYMBOL MIN. MAX UNIT NOTE
INPUT LEAKAGE CURRENT I IO l 0 A
OVSVINSQSV. All other pins not under test=0V I(L) "
OUTPUT LEAKAGE CURRENT I 10 10 A
ovsvOUT s5.5v, OutputDisable WL) "
OUTPUT "H" LEVEL VOLTAGE
von 2.4 - V
[OUT = - 2mA
T "L'' LEVEL V AGE
OUTPU n 0LT VOL - 0.4 V
IOUT = 2mA
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
ELECTRICAL CHARACTERISTICS AND RECOMMENDED A.C.
OPERATING CONDITIONS (Vcc = 5V i 10%, Ta = 0~70°C)(N0tes: 5, 6, 7)
SYMBOL PARAMETER -80 -10 UNIT NOTE
MIN. MAX. MIN. MAX
tsu: Random Read or Write Cycle Time 150 180
teMw Read-Modify-Write Cycle Time 195 235
tec Fast Page Mode Cycle Time 50 55
teeMw Fast Page Mode Read-Modify-Write Cycle 90 100
[RAC Access Time from Ris 80 100 8,14
(AA Access Time from Column Address 45 50 8,14
(CAC Access Time from m 25 25 8,15
tCPA Access Time from t5AT; Precharge 45 50 8,15
top]: Output Buffer Turn-Off Delay 0 20 0 20 10
IT Transition Time (Rise and Fall) 3 35 3 35 7
trw IEW; Precharge Time 60 70
IRAS ITA-S Pulse Width 80 10000 100 10000
‘RASP m Pulse Width (Fast Page Mode Only) 80 100000 100 100000
:RSH RTAS Hold Time 25 25
ICSH CA9 Hold Time 80 100
[CAS m Pulse Width 25 10000 25 10000
IRCD 'TAS to m Delay Time 20 55 20 75 14
{RAD EM to Column Address Delay Time 15 35 15 50 ns 14
IRAL Column Address to m Lead Time 45 50
tou, tTAS to ITA-S" Precharge Time 10 10
ICPN m Precharge Time 10 10
tcp m Precharge Time (Fast Page Mode) 10 10
tASR Row Address Set-Up Time 0 O
[RAH Row Address Hold Time 10 10
tASC Column Address Set-Up Time 0 0
ICAH Column Address Hold Time 15 15
[AR Column Address Hold Time referenced to R-AS 55 70
IRCS Read Command Set-Up Time
[RCH Read Command Hold Time 0 0 11
[RRH Read Command Hold Time referenced to m 0 0 ll
(WCH Write Command Hold Time 15 15
1WCR Write Command Hold Time referenced to R-AS 55 70
twp Write Command Pulse Width 15 15
[RWL Write Command to m Lead Time 20 25
ICWL Write Command to Ch-s Lead Time 20 25
C-118 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SYMBOL PARAMETER -80 -10 UNIT NOTE
MIN. MAX MIN. MAX
tDS Data Set-Up Time 0 0 12
[DH Data Hold Time 15 15 12
tom Data Hold Time referenced to RTS 55 70
twcs Write Command Set-Up Time 0 0 13
tRWD R-Ag to WE Delay Time 100 130 13
tAWD Column Address to WE Delay Time 65 80 13
tevo TWT to WE Delay Time 45 55 13
trm: Data to tTAS Delay Time
tDZO Data to tTr! Delay Time 0 ns
tOEA Access Time from o-E 20 25 8
IOEZ Output Buffer Tum-off Delay from (TE 0 10 0 20 10
tOED W to Data Delay Time 10 20
tom tTE Command Hold Time 10 20
tROH It-Eg Hold Time referenced to W 15 15
ttse tTM Set-Up Time for m Before m Cycle 10 10
tCHR m Hold Time for TATI Before CAT; Cycle 10 10
tRpC ITA''t- Precharge to tTAB- Active Time 0 0
tREF Refresh Period 8 8 ms
tWSR WIT Set-Up Time 0 0
tRWH WtT Hold Time 15 15
tFSR DSF Set-Up Time referenced to R-Ag 0 0
tRFH DSF Hold Time referenced to Wm 15 15
tFHR DSF Hold Time referenced to mm 55 70
thc DSF Set-Up Time referenced to m 0 0
tcrm DSF Hold Time referenced to tTAS 15 15
tMS Write-Per-Bit Mask Data Set-Up Time 0 0
tMH Write-Per-Bit Mask Data Hold Time 15 15
tms ET High Set-Up Time 0 0 ns
tTHH DT High Hold Time 15 15
[TLS BT Low Set-Up Time 0 0
tTLH m' Low Hold Time 15 10000 15 10000
tRTH BT Low Hold Time referenced to ICM 65 10000 80 10000
(Real Time Read Transfer)
tATH W Low Hold Time referenced to Column 30 30
Address (Real Time Read Transfer)
tcm DT Low Hold Time referenced to Ch-s 25 25
(Real Time Read Transfer)
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SYMBOL PARAMETER -80 -10 UNIT NOTE
MIN. MAX. MIN. MAX.
IESR E Set-Up Time referenced to R-AS 0 0
IREH SE Hold Time referenced to Itis 15 15
hw, W to RTXS Precharge Time 60 7O
tTP W Precharge Time 20 30
tRSD m to First SC Delay Time (Read Transfer) 80 100
t ASD Column Address to First SC Delay Time 45 50
(Read Transfer)
ICSD m to First SC Delay Time (Read Transfer) 25 25
ITSL Last SC to Ft Lead Time 5 5
(Real Time Read Transfer)
ITSD DT to First SC Delay Time (Read Transfer) 15 15
tSRS Last SC to rtTCs Set-Up Time (Serial Input) 30 30
tSRD EM to First SC Delay Time (Serial Input) 25 25
‘SDD R-AS" to Serial Input Delay Time 50 50
ISDZ Serial Outplft Buffer Turn-off Delay from IThTi 10 50 10 50 10
(Pseudo Write Transfer)
ISCC SC Cycle Time 30 30
tsc SC Pulse Width (SC High Time) 10 10
tSCp SC Precharge Time (SC Low Time) 10 10
ISCA Access Time from SC 25 25 ns 9
tsou Serial Output Hold Time from SC 5
tSDs Serial Input Set-Up Time 0 0
tson Serial Input Hold Time 15 15
ISEA Access Time from STE 25 25 9
tse E Pulse Width 25 25
ISEP E Precharge Time 25 25
ISEZ Serial Output Buffer Turn-off Delay from E 0 20 0 20 IO
tsze Serial Input to SE Delay Time 0 0
tszs Serial Input to First SC Delay Time 0 0
tsws Serial Write Enable Set-Up Time 0 0
[SWH Serial Write Enable Hold Time 15 15
ISWIS Serial Write Disable Set-Up Time 0 0
tswm Serial Write Disable Hold Time 15 15
tSTS Split Transfer Set-Up Time 30 30
13TH Split Transfer Hold Time 30 30
tsoo SC-QSF Delay Time 25 25
ITQD BT-OSF Delay Time 25 25
ICQD cis-OSF Delay Time 35 35
[RQD m-QSF Delay Time 75 90
C-120 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
NOTES:
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
All voltage are referenced to Vss.
These parameters depend on cycle rate.
These parameters depend on output loading. Specified values are obtained with the output open.
An initial pause of 200ps is required after power-up followed by any 8 RAS cycles (ID-T/WE "high") and
any 8 SC cycles before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS before RAS initialization cycles instead of 8 RAS cycles are required.
AC measurements assume tT = 5ns.
Vm (mm and VIL (mm are reference levels for measuring timing of input signals. Also, transition times
are measured between Vm and VIL.
RAM port outputs are measured with a load equivalent to 1 TTL load and lOOpF.
DOUT reference levels : VOH / Vor. = 2.0V / 0.8V.
SAM port outputs are measured with a load equivalent to l TTL load and 30pF.
DOUT reference levels : VOH / VOL = 2.0V /0.8V.
[OFF (max.p 1052 Imax.)' tsoarmac) and tSEZ (mam define the time at which the outputs achieve the open
circuit condition and are not referenced to output voltage levels.
Either tRCH or tRRH must he satisfied for a read cycles.
These parameters are referenced to CAS leading edge of early write cycles and to VB / WE leading
edge in O-E-controlled write cycles and read-modify-write cycles.
twcs, IRWD. ICWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If twcs Z twcs (mm). the cycle is an early write cycles and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; lftRwok tRWD (mm. ICWDZ
tcwD (min.) and tAwDZ tAWD (min.) the cycle is a read-modify-write cycle and the data out will contain
data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of
the data out (at access time) is indeterminate.
Operation within the tRCD mm" limit insures that tRAC (man can he met.
tRCD (max.) is specified as a reference point only : If tRCD is greater than the specified
tRCD (mac) limit, then access time is controlled by tCAC.
Operation within the {RAD (mam limit insures that IRAC (mar) can be met. tRAD (mm is specified as a
reference point only: If IRAD is greater than the specified [RAD mm.) limit, then access time is controlled
by IAA.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-121
TC528128B
TIMING WAVEFORM
READ CYCLE
now COLUMN
A0~A8 Aoonsss Aoonsss
VTB/WE
W1/l01
~W8ll08
L OUT ----_----- VALID DATA-OUT
: "H'' or "L"
C-122 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
WRITE CYCLE (EARLY WRITE)
W1/IO1
~W8/l08
L- OUT
ADDRESS
COLUMN
ADDRESS
WMI DATA op/il',,
Vor, -
VOL - OPEN
: "H" or "L"
*1 T277tTTt" W1/IOl~W8/108 Cycle
0 WMI data Write per bit
1 Don't Care Normal Write
WMI data 0: Write Disable
l: Write Enable
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
WRITE CYCLE (6E CONTROLLED WRITE)
T"-- IN
W1IIOI
~W8/l08
L_.. OUT
ADDRESS
WMI DATA
COLUMN
ADDRESS
VALI D
DATA-IN
VOL - OPEN
'Cie'? : "H" or "L"
*1 WBW Wl/IOl~W8/108 Cycle
0 WMl data Write per bit
1 Don't Care Normal Write
WMl data 0: Write Disable
l: Write Enable
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
READ-MODIFY-WRITE CYCLE
A0-A8 "
DSF Vic
l" IN " -
WII101
-W8/IO8
our Voc-...
ROW COLUMN
ADDRESS ADDRESS
WMI DATA
''jg,tt'cit' .' "H" or "c"
*1 m" TCE Wl/IOl~W8/108 Cycle
0 WMl data Write per bit
l Don't Care Normal Write
WMl data 0: Write Disable
l: Write Enable
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
F AST PAGE MODE READ CYCLE
AO- A8
WE/WE Ihr,
T- IN "
WI/lOl tcac
~W8/l08
l-ou, x0"
oAm/our DATAZ-OU DATA-OU
:"H" or "L''
C-126 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
AO-All
157/6!
m DATAAN DATA-m DATA-IN
W1IIOI
~W8/l08
L-our Il,',: - OPEN
'trtbfgi :"H" or "L'
*1 Wri/WE W1/IO1-W8/IO8 Cycle
0 WMI data Write per bit
1 Don't Care Normal Write
WMl data 0: Write Disable
1: Write Enable
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-127
TC528128B
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
W1/IOI
~W8/l08
',2f(g,,tgi, : "H" or "L"
*1 WW w 1/10 1 '-W8/IO8 Cycle
0 WMI data Write per bit
I Don't Care Normal Write
WMI data 0: Write Disable
1: Write Enable
C-128 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
RAS ONLY REFRESH CYCLE
tttas tio
liM [e H h, y N,
too -ty'c mm.“
a [e -..'.] a Ncyr
l tasrt anpu
At)--A8 'j: --iiiiii)iisthas aEiEiiEEEiiEiE5EEiiE)CCD4i,
3% «H. \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
I trra ttsm
2a" 1jCfgfiift 1et',fi't?ift't'i)iiii 'ft,fij5j
t SR En
F " H§V A? /'' //''
DS " f5 - A
WI /IOt Vow I
158:8 <9 I 022
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-l mm
TC528128B
CAS BEFORE RAS REFRESH CYCLE
-s t: --Lrr-a'-"tr.r;ss, teat \_
m x: _-.-..-.-----,---.-:.,'-':'-''--'') tco 'lagEigiiEiiiiiiigEE
Wi5ti7W "ve fl//////////////////////////////////////////////////////////////
W1/101 Vor, -
~wtu ©8 VOL - OPEN
Note:A0-A8 '' Don't Care CH'' or 'L') (gfjfgi' :"H" or "L''
C-130 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
HIDDEN REFRESH CYCLE
ROW COLUMN
A0-A8 ADDRESS ADDRESS
W1 / KM
-W8/ IO8 VALID DATA-OUT
1jjffi"e; .. "H" or "L'
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-131
TC528128B
LOAD COLOR REGISTER CYCLE
A0-A8 ADDRESS
ETIESE
T- COLOR DATA-IN
w1/IOI (Delayed Write)
~W8/ |08
COLOR DATA-IN
(Early Write)
yCtti'fft' t "H" or "L"
C-132 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
READ COLOR REGISTER CYCLE
WI/lOl
~W8/l08
. x :: /---t-"---h_,
----vii",', -", tttttr 'ss, Iii? ( J: m 'su,
---tiiiiiisiat:iN $>W/////////////////////////////////////
: 4 VAUDOW y---
: "H'' or "L"
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
FLASH WRITE CYCLE
A0~A8 ROW ADDRESS
f- IN WMI DATA
w1/I01
~we/Ioa
L.- om Vou- OPEN
: "H" or "L"
WMl Cycle
0 Flash Write Disable
1 Flash Write Enable
C-134 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
BLOCK WRITE CYCLE
A0 -A8
W1/IO1
~W8/IOB
" ROW ADD.
ESE; (A2c~A7Q
: "H" or "L"
*1 WBW *2 W1/IO1-W8/IO8 Cycle
0 WMI data Masked Block Write
1 Don't Care Block Write (Non Mask)
WMI data 0: Write Disable
1: Write Enable
*3 COLUMN SELECT
WI/lOl -Colurnn0(Nc=0,Aoc=0 wnnon
W2/102 - Column 1 (Am: O, Aoc =1 = O
W3/IO3 - Column 2(A1c = l, Aoc = 0 Disable
W4/IO4 - Column 3 (AIC =1,Aoc = l
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
PAGE MODE BLOCK WRITE CYCLE
A0--A8
WI/lOl
~W8/R08
:"H'' or "L"
*1 WW *2 Wl/IOl--W8/IO8 Cycle
0 WMI data Masked Block Write
1 Don't Care Block Write (Non Mask)
WMI data 0: Write Disable
I: Write Enable
*3 COLUMN SELECT
WI/IOI - Colume 0 (Alc = o, Aor: = 0
W2/IO2 - Column l (AIC = o, Aoc = l
W3/IO3 - Column 2 (AIC = l, Mar-- O
W4/IO4 - Column 3 (A1C = l, Aoc: = l
Wn/lOn
Disable
C-136 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
READ TRANSFER CYCLE (Previous Transfer is WRITE TRANSFER CYCLE)
AO-N) ROW ADDRESS SAM STARTADDRESS
AO-A? : TAP
W1/IO1
~W8/IOS
SC _ Inhibit Rising Transient
IN DATAAN
QSF TAP MSB (A7)
Note ', 7 = "
: "H" or "L"
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-137
TC528128B
REAL TIME READ TRANSFER CYCLE
tase tRAM
V.” ROW (
AO-N, " ADDRESS / SAM START
AW-A7 ' TAP
twsn tttvim
WI/lOl Vor,
~W8/l08 Voc.-
SC VIL
l [N " tsca
5'01 tso"
l Von VALID VALID VALID VALID VALID
OUT VOL - DATA-OUT DATA-OUT DATA-OUT DATA-OUT onmour
Previous Row Data New Row Data
Vor, -
QSF Voc - TAP MSB (A7)
Note : S? = "
',"kggfj, : "H" or "c"
C-138 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SPLIT READ TRANSFER CYCLE
A0 ~AB
ROW SAM START
ADDRESS ADDRESS n
twsa A0-A6 : TAP
S n n+1 n+2 12 126
7) (n+128) (n+129) (no 130) (254)
\\\\\\\
125 126
(126) (127) (n . 128) nn, o 129) m", #1 S3) (254)
Lower SAM 0 - 127
Upper SAM 128-- 255
Note : S? = "
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
:"H" or "u"
TC528128B
PSEUDO WRITE TRANSFER CYCLE
NF. A8
~W8/l08
--SIO8
't ROW ADDRESS SAM START ADDRESS
AO~A7 '. TAP
" Inhibit Rising Transient
VA LID
DATA-OUT
VALI D
DATA-OU
OPEN ""-'t-""-""""'"
VOL - ', TAP M58 (A7)
Serial Output Data -
- Serial Input Data
'fig?) : "H" or "L"
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
WRITE TRANSFER CYCLE
A0--A8 v: ROW ADDRESS SAMSTARTADDRESS
A0~A7iTAP
WEIWE Va.
57/65 7,'l
DSF v:
W1/IOI v0.4
~wsnoa VOL-
SC " Inhibit Rising Transient
g! VII.
VIII VALID VALID
T- IN " DATA-IN DATA-IN TA-IN
l-. OUT OH
Vor, -
ttsr Vou - TAP MSB (A7)
---- New Row Data
Previous ---'
Row Data
WM1 data: 0: Transfer Disable 'bTddi : "H" or "L''
1: Transfer Enable
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-141
TC528128B
SPLIT WRITE TRANSFER CYCLE
A0--A8
~W8I|08
--SIO8
ADDRESS
ADDRESS
A0-A6 : TAP
(5%?) 6%)
n nel no;
((19128) (n0129) (rt-l 0)
tt n 1 n +
" J...d5g, (n o 128) (n '.1a's, tn o 1301 ..............
......... ...........
Lower SAM 0 - 127
Upper SAM 128 - 255
:"H" or "c"
Note : TT s "
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SERIAL READ CYCLE (gii=su)
trfH52
“MSW ttroi
DATA-OUT
2iiiiiiEEERjjjiiEiEiiiiig'
DATA-OUT DATA-OUT
Nate 2 {El "
SERIAL READ CYCLE (STE" Controlled Outputs)
DATA-OUT
ISCA tsta
ATA-OUT
DATA-OUT
Cke'ifk :"H" or "c"
ttms trroe
"ragEgligiiiaiiiaiiigga
ISCL 7 Bcc
_.,tstu Asc, Agar -.,ttC
/ i \ M I, /
Instr "tsci" "tso, "tso,
5m. tsta r-tacts Isa.
£50): 7 +15“ tsot, Js-te.,.,
VALID VALID F VALID VALID VALID
DATA-OUT X DATA-OUT F-OPEN -f. DATA-OUT X DATA-OUT x ATA-OUT
ggigi' : "H'' or "L"
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-143
TC528128B
SERIAL
-SIt38
SERIAL
WRITE CYCLE (gii---vrL)
tms mm
33/ tr%EtitEEiiiiitiji.iiiEiiiii
tscc tscc SCC, tscc, t tscc
tsc ttt . tsc tsc , " ,
Sh" - / V i K
" - tso" tson [£5014 tsou M tsrm
_ tTir
"tso I tso, "t 'ir Asc, p
tsos _ " "
tsos L A_ tsos L tsos A tsuns
Ihr, - VALID h VALID A VALID Ar VALID Ae VALID
" - T DATA-IN,- DATA-IN, DATA-INS'-' .. t'ATAuNt1 , DATA-IN
Note : 3?: " [tig, :"H'' or "L''
WRITE CYCLE (iiii Controlled Inputs)
Vlt. -
VALI D
DATA-IN
OATA-IN
wa : "H'' or "L"
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
PIN FUNCTION
ADDRESS INPUTS t A0 _ As
The 17 address bits required to decode 8 bits of the 1,048,576 cell locations within the dynamic RAM
memory array of the TC528128B are multiplexed onto 9 address input pins (Air-Ae). Nine row address bits are
latched on the falling edge of the row address strobe (RAS) and the following eight column address bits are
latched on the falling edge of the column address strobe (W).
ROW ADDRESS STROBE , RAS
A random access cycle or a data transfer cycle begins at the falling edge of m. m is the control input
that latches the row address bits and the states of CM, 15MrE, IIB/WE, E and DSF to invoke the various
random access and data transfer operating modes shown in Table 2. KM has minimum and maximum pulse
widths and a minimum precharge requirement which must be maintained for proper device operation and data
integrity. The RAM port is placed in standby mode when the RAS control is held "high".
COLUMN ADDRESS STROBE : CAS
CATS is the control input that latches the column address bits and the state of the special function input DSF
to select, in conjunction with the TCA-S control, either read / write operations or the special block write feature
on the RAM port when the DSF input is held "low" at the falling edge of EEg. Refer to the operation truth table
shown in Table l. W has minimum and maximum pulse widths and a minimum precharge requirement which
must be maintained for proper device operation and data integrity. CTG also acts as an output enable for the
output buffers on the RAM port.
DATA TRANSFER/OUTPUT ENABLE t iii/6ii
The DT/C-E input is a multifunction pin. When DT/tFE is "high" at the falling edge of RAS, RAM port
operations are performed and Fyr/trE is used as an output enable control. When the -D"ryo-E is "low" at the falling
edge of RAS, a data transfer operation is started between the RAM port and the SAM port.
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TC528128B
WRITE PER BIT/WRITE ENABLE ..CrB/Wii;
The WtT/iW input is also a multifunction pin. When lt/g/WE is "high" at the falling edge of m, during
RAM port operations, it is used to write data into the memory array in the same manner as a standard DRAM.
When W/WE is "low'' at the falling edge of m, during RAM port operations, the write-per-hit function is
enabled. The m/w-E input also determines the direction of data transfer between the RAM array and the serial
register (SAM). When TIP WI is "high" at the falling edge of m, the data is transferred from RAM to SAM
tread transfer). When VB/Wi is "low" at the falling edge of m, the data is transferred from SAM to RAM
(masked-write transfer).
WRITE MASK DATA/DATA INPUT AND OUTPUT : w1/101~w8/108
When the write-per-bit function is enabled, the mask data on the Wi/IOi pins is latched into the write mask
register (WMl) at the falling edge of m. Data is written into the DRAM on data lines where the write-mask
data is a logic "l". Writing is inhibited on data lines where the write-mask data is a logic "O''. The write-mask
data is valid for only one cycle. Data is written into the RAM port during a write or read-modify-write cycle.
The input data is latched at the falling edge of either CA-S or Wm/WTC, whichever occurs late. During an early-
write cycle, the outputs are in the high impedance state. Data is read out ofthe RAM port during a read or read-
modify-write cycle. The output data becomes valid on the Wi/IOi pins after the specified access times from m,
m. BTytrE and column address are satisfied and will remain valid as long as tTA-s and D-T/O-E are kept "low".
The outputs will return to the high-impedance state at the rising edge ofeither m or BT/UE, whichever occurs
first.
SERIAL CLOCK l SC
All operations of the SAM port are synchronized with the serial clock SC. Data is shifted in or out of the
SAM registers at the rising edge of SC. In a serial read, the output data becomes valid on the SIO pins after the
maximum specified serial access time tSCA from the rising edge of SC. The serial clock SC also increments the
8-bits serial pointer (7-bits in split register mode) which is used to select the SAM address. The pointer address
is incremented in a wrap-around mode to select sequential locations after the starting location which is
determined by the column address in the read transfer cycle. When the pointer reaches the most significant
address location (decimal 255), the next SC clock will place it at the least significant address location (decimal
0). The serial clock SC must he held at a constant Vm or VIL level during read / pseudo write / write transfer
operations and should not he clocked while the SAM port is in the standby mode to prevent the SAM pointer
from being incremented.
C-146 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SERIAL ENABLE l 7
The E input is used to enable serial access operation. In a serial read cycle, E is used as an output control.
In a serial write cycle, SE is used as a write enable control. When TE is "high", serial access is disabled,
however, the serial address pointer location is still incremented when SC is clocked even when E is "high".
SPECIAL FUNCTION CONTROL INPUT t DSF
The DSF input is latched at the falling edge of RAS and CAS and allows for the selection of various
random port and data transfer operating modes. In addition to the conventional multipon DRAM, the special
features consisting of flash write, block write, load color register and split read / write transfer can be invoked.
SPECIAL F UNCTION OUTPUT t QSF
QSF is an output signal which, during split register mode, indicates which half of the split SAM is being
accessed. QSF "low" indicates that the lower split SAM (Bit 0~127) is being accessed and QSF "high" indicates
that the upper split SAM (Bit 128--255) is being accessed. QSF is monitored so that after it toggles and after
allowing for a delay of tsrs, split read / write transfer operation can be performed on the non-active split SAM.
SERIAL INPUT/OUTPUT l SIOl~SIOS
Serial input and serial output share common I/O pins. Serial input or output mode is determined by the
most recent read, write or pseudo write transfer cycle. When a read transfer cycle is performed, the SAM port
is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from
output mode to input mode. During subsequent write transfer cycle, the SAM remains in the input mode.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-147
TC528128B
OPERATION MODE
The RAM port and data transfer operating of the TC524258B are determined by the state of CAS, BThrE,
WW, SE and DSF at the falling edge of RAS and by the state of DSF at the falling edge of CAS. The Table
l and the Table 2 show the operation truth table and the functional truth table for a listing of all available RAM
port and transfer operation, respectively.
V _-------- "ss Table l. Operaton Truth Table
CAS falling edge t 's, \
I Cr- _ - _-_,---spsirr-- - ' ' ' - - ’*'**'—‘—"—— - r - - i - - - " - _
RAS falling edge t I 's, 0 () I
- J } J
V - :_ .7; - \Ds _----- 7 . T - - .____.._A_ 7 - 7 ..
\CAS 'vIrTrt,f,/c,, WB_7\SE "s, o 1 1
V N \05 .WE 's, x
7 -F--, ; r,----']-----, 7 7 7 - - - - 7:7. 2 77 _7 7 7 - -
O 1 * . * CAS before RAS Refresh 7 _-r ~:
_ . -_ _ - 7 77777777 ------,----i-"- 7M - 47:7, 7 7 H . ' 7 -
l 1 _ 0 0 0 Masked Write Transfer Split Write Transfer with Masked Write Transfer Split Write Transfer with
, ---+---- "f" - 7 - F” ___i,, - - V
l 0 0 1 f Pseudo Write Transfer Mask l Pseudo Write Transfer Mask
_ 7 7 V --. - _ - - ,iiiiwfi r _ _ _
I l 0 F I [ * Read Transfer Split Read Transfer l Read Transfer Split Read Transfer
_-rt-r---) i -' - _- i - M - -
l l i 0 1 . iRead/Write per Bit Masked Flash Write 7 Masked Block Write Masked Flash Write
l l 1 F 1 * TRead/Write Load Color i Block Write ; Load Color
2. Functional Truth Table
R-A-g-i cis 1 Address wno Register
Function - ' - _ - - ' M2:
CAS BT/OE WW DSF s_E DSF RA , CAS , RAS , CAS , 3;? -,- WMI Color
CAS before RAS Refresh 0 * b ' * - * * - - - _ -
Masked Write Transfer 1 o 0 o o * Row TAP WMI . * WMI tf -
Pseudo Write Transfer 1 0 0 0 I * Row TAP * * . -
Split Write Transfer l 0 0 l * * Row TAP WMI - * WMI tf -
Read Transfer 1 0 l 0 * * Row TAP * * * - 7
Split Read Transfer 1 0 1 l * * Row TAP * * * 7
Write per Bit l l 0 0 * 0 Row Column WMI DIN WMl use -
Column Column Load
' l . W 7 WMI
Masked Block Write l 0 0 I Row A2C-7C Ml Select use use
Masked Flash Write 1 l 0 I * * Row a WMI _ * WMI u; use
Read Write 1 I I O * 0 Row Column * - DIN -
Column Column
. t * _ 7
Block Write 1 l l 0 1 Row A2C-7C Select use
Load Color l l l l * * Row * * 7 Color - - Load
* : "O" or "l" ' TAP:
SAM start address , : not used
If the special function control input (DSF) is in the "low" state at the falling edges of ICM and tTM, only
the conventional multipon DRAM operating features can be invoked: C-AS-before-AA-g refresh, write transfer,
pseudo-write transfer, read transfer and read write modes. If the DSF input is "high" at the falling edge of m.
special features such as split write transfer, split read transfer, flash write and load color register can be invoked.
If the DSF input is "low" at the falling edge of m and "high" at the falling edge of m, the block write special
feature can be invoked.
C-148 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
RAM PORT OPERATION
FAST PAGE MODE CYCLE
Fast page mode allows data to be transferred into or out of multiple column locations of the same row by
performing multiple m cycle during a single active RTE cycle. During a fast page cycle, the EM signal may
be maintained active for a period up to 100 “seconds. For the initial fast page mode access, the output data is
valid after the specified access times from m. m, column address and DT/W. For all subsequent fast page
mode read operations, the output data is valid after the specified access times from tWg, column address and
BT/UE, When the write-per-bit function is enabled, the mask data latched at the falling edge of FCM" is
maintained throughout the fast page mode write or read-modify-write cycle.
RAS-ONLY REFRESH
The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished by
performing a memory cycle at each of the 512 rows in the DRAM array within the specified 8ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most easily
accomplished with “W-Only“ cycle.
CAS-BEFORE-RAS REFRESH
The TC528128B also offers an internal-refresh function. When Chg is held "low" for a specified period
(tCSR) before R_AS goes "low", an internal refresh address counter and on-chip refresh control clock generators
are enabled and an internal refresh operation takes place. When the refresh operation is completed, the internal
refresh address counter is automatically incremented in preparation for the next CTG-before-R-AT; cycle. For
successive m-before-m refresh cycle, as can remain "low" while cycling m.
HIDDEN REFRESH
A hidden refresh is a CA-S-before-R-AS refresh performed by holding m "low" from a previous read
cycle. This allows for the output data from the previous memory cycle to remain valid while performing a
refresh. The internal refresh address counter provides the address and the refresh is accomplished by cycling
R-A-g after the specified m-precharge period (Refer to Figure l).
"''"'-Merttory Cycle ----_--- Refresh Cycle ----_---- Refresh Cycle ---
m --"-"i" (t, C-N, r“
m --] J
W1/l01
W8/lOB --------( Valid Data Output _------
Figure 1. Hidden Refresh Cycle
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TC528128B
WRITE-PER-BIT FUNCTION
The write-per-bit function selectively controls the internal write-enable circuits of the RAM port. When
"w-ly / W is held "low" at the falling edge of R-AS, during a random access operation, the write-mask is enabled.
At the same time, the mask data on the w,. / IO,. pins is latched onto the write-mask register (WM 1 ). When a "O''
is sensed on any of the w,. I IOi pins, their corresponding write circuits are disabled and new data will not be
written, When a "I'' is sensed on any of the Wi / IO, pins, their corresponding write circuits will remain enabled
so that new data is written. The truth table of the write-per-bit function is shown in Table 3.
Table 3. Truth table for write-per-bit function
At the falling edge of RAS
- --_- - - Function
CAS DT/OE WB/WE Wi/IOi (i=1~8)
H H H * Write Enable
1 Write Enable
H H . L
0 Write Mask
An example of the write-per-bit function illustrating its application to displays is shown in Figures 2 and 3.
m ----L_r-----
Ao-At wL m (oluinnjm Cff,
mm: ac:Lzac.,'Lzzzzz,
W./|01 a,eit.aiaait.iaiaiaaa
wznoz iEr'iiir7riarri',riiNaam
Wa/tth aLeiLaaiiaitaaaaaa
wmo. aritrmaaaie.ezaaz
Wsllos aevuazataaiiazia
nglos zrvrtrear-T..tvcceaaiai
Wr/lor iaaLaaiataiazaia
Wal'oa Writ. o/ tite
L. Write
w.IIo.-L '. Write Mate
W,IIO'-H : Write
Figure 2. Write-per-bit timing cycle
CRT Display
IOIOIOlOiOIOIOIOI
_ fL "o" Writ.
No Write (Masha!)
"t" Write
No Wm. (Muted)
'0. Write
No Write (Muted)
"l" Write
No Wm. (Muted)
Figure 3. Corresponding bit-map
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
LOAD COLOR REGISTER/READ COLOR REGISTER
The TC528128B is provided with an on-chip 8-bits register (color register) for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM l/O blocks. The load
color register cycle is initiated by holding CTS, WW, trt/O-E and DSF "high" at the falling edge of KA-S.
The data presented on the Wi/IOi lines is subsequently latched into the color register at the falling edge of either
m or WW. whichever occurs last. The data stored in the color register can be read out by performing a
read color register cycle. This cycle is activated by holding m. Tim/WE, BThrE and DSF "high" at the falling
edge of kis and by holding WW "high" at the falling edge of tTAS and throughout the remainder of the
cycle. The data in the color register becomes valid on the Wi/IOi lines after the specified access times from IrAT;
and ltr/O-E are satisfied. During the load/read color register cycle, valid Ao-vt, row addresses are not required.
but the memory cells on the row address latched at the falling edge of R-Af; are refreshed.
FLASH WRITE
Flash write is a special RAM port write operation which in a single R cycle, allows for the data in the
color register to be written into all the memory locations of a selected row. Each bit of the color register
corresponds to one of the DRAM 1/0 blocks and the flash write operation can be selectively controlled on an I/
0 basis in the same manner as the write-per-bit operation.
A flash write cycle is performed by holding CAS "high", Wg/WE "low" and DSF "high" at the falling
edge of m. The mask data must also be provided on the Wi/IOi lines at the falling edge of It-A-if in order to
enable the flash write operation for selected I/O blocks (Refer to Figure 4 and 5).
Flash write is most effective for fast plane clear operations in frame buffer applications. Selected planes
can be cleared by performing 512 flash write cycle and by specifying a different row address location during
each flash write cycle (Refer to Figure 6). Assuming a cycle time of 180ns, a plane clear operation can be
completed in less than 92.2 “seconds.
W ---is.-.-.,.,-,...,.-r"---
Am ac''tzazzzaazzzaz
'iNlitWt aci.sazzzzzzazaa
DSF zriraazzzzazzza
WM1 H: Write
L: Write Inhibit
Figure 4. Flash Write Timing
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TC528128B
Selected
Row - fffffffff' ffffffffff' ////// /////////
Register ------- +0 Cl L1 Cl Cl a El
R l K I K l
r J" f
Write Enable Write Disable
Figure 5. Flash Write
Buffer N,
"ss' Clear
Figure 6. Plane clear application example
BLOCK WRITE
Block write is also a special RAM port write operation which, in a single RAS cycle, allows for the data
in the color register to be written into 4 consecutive column address locations starting from a selected column
address in a selected row. The block write operation can be selectively controlled on an I/O basis and a column
mask capability is also available.
A block write cycle is performed by holding m, [717% "high" and DSF "low" at the falling edge of
R-AS and by holding DSF "high" at the falling edge of m. The state of the Wm/iw input at the falling edge
of EhT; determines whether or not the 1/0 data mask is enabled (1lrB/lrE must be "low " to enable the I/O data
mask or "high" to disable it). At the falling edge of R-AS, a valid row address and I/O mask data are also
specified. At the falling edge of m, the starting column address location and column mask data must be
provided. During a block write cycle, the 2 least significant column address locations (ADC and AlC) are
internally controlled and only the six most significant column addresses (A2C-ATC) are latched at the falling
edge of m. (Refer to Figure 7).
An example of the block write function is shown in Figure 8 with a data mask on Wl/IOI, W 4/ 104, W6]
106, W7/ IO, and column 2. Block write is most effective for window clear and fill operation in frame buffer
applications, as shown in the examples in Figure 9.
C-152 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
5‘5 --i---------i ','. C'-'-""-
Aa-Att 2itelNEWc_iLrFtiTuc_sec_EffWWfWEzZl
I?;~\ i
WWW? 2acCl(lfel
W1/IO1 :ColumnD
wzno, :ColumnI H :Write
[H :No Mask J w3/1o3 :Column2 L :Write Mask
L :Mask Enable wmo. :Column3
Figure 7. Block Write Timing
Mask Data c:clrerptn R2293; Colzmn "r" Colgmn Coigmn
W1II01 0 1 0 Mask
Wa/IO: 1 1 o c::)
w3/103 1 o 1
W4/IO. 0 1 I Mask
Wsllos 1 - 1
1NstlOs o - 1
Wrflth 0 - 0
wwos 1 - o
Figure 8. Example of Block Write Operation
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TC528128B
+1753ng
_-ttij,,
-eta.iz""
Figure 9. Examples of Block Write Application
FAST PAGE MODE BLOCK WRITE CYCLE
Fast page mode block write can be used to perform high speed clear and fill operations. The cycle is
initiated by holding the DSF signal "low" at the falling edge of R-Ag and a fast page mode block write is
performed during each subsequent tTAff cycle with DSF held "high" at the falling edge of m.
If the DSF signal is "low" at the falling edge of tTM, a normal fast page mode read / write operation will
occur. Therefore a combination of block write and read / write operations can be performed during a fast page
mode block write cycle. Refer to the example shown in Figure 10.
“W " f-
m '.._..co..c.si..irisr?ihiri..rj..r,
DsF--lithrtnrtn d'nrtl
L " MU, J
Block Write Cycle Read/Write Cycle Block Write Cycle
Figure 10. Fast Page Mode Block Write Cycle
C-154 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
SAM PORT OPERATION
The TC528128B is provided with a 256 words by 8 bits serial access memory (SAM) which can be
operated in the single register mode or the split register mode.
SINGLE REGISTER MODE
When operating in the single register mode, high speed serial read or write operations can be performed
through the SAM port independent of the RAM port operations, except during read / write / pseudo-write
transfer cycles. The preceding transfer operation determines the direction of data flow through the SAM port. If
the preceding transfer operation is a read transfer, the SAM port is in the output mode. If the preceding transfer
operation is a write or pseudo write transfer, the SAM port is in the input mode. The pseudo write transfer
operation only switches the SAM port from output mode to input mode; Data is not transferred from SAM to
Serial data can be read out of the SAM port after a read transfer (RAM-MMM) has been performed. The
data is shifted out of the SAM port starting at any of the 256 bits locations.
The TAP location corresponds to the column address selected at the falling edge of tTig during the read
transfer cycle. The SAM registers are configured as circular data registers. The data is shifted out sequentially
starting from the selected tap location to the most significant bit and then wraps around to the least significant
bit, as illustrated below.
Start.address : Tap location
o 1 2 ------ i.,..- ------------------- 253 254 255 -
Subsequent real-time read transfer may be performed on-the-fly as many times as desired, within the
refresh constraints of the DRAM array. Simultaneous serial read operation can be performed with some timing
restrictions. A pseudo write transfer cycle is performed to change the SAM port from output mode to input mode
in order to write data into the serial registers through the SAM port. A write transfer cycle must be used
subsequently to load the SAM data into the RAM row selected by the row address at the falling edge of ARS.
The starting location in the SAM registers for the next serial write is selected by the column address at the falling
edge of C73. The truth table for single register mode SAM operation is shown in Table 4.
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TC528128B
Table 4. Truth Table for SAM Port Operation
SAM PORT D-T/OT! at the -
OPERATION falling edge of RVs SC SE FUNCTION Preceded by a
. L Enable Serial Read
Serial Output Mode . . Read Transfer
H Disable Serial Read
. L Enable Serial Write '
Serial Input Mode H . . . Write Transfer
H Disable Serial Write
. - L Enable Serial Write .
Serial Input Mode - . . . Pseudo Write Transfer
H Disable Serial Write
SPLIT REGISTER MODE
In split register mode, data can be shifted into or out of one half of the SAM while a split read or split write
transfer is being performed on the other half of the SAM. A normal (Non-split) read / write / pseudo write
transfer operation must precede any split read / write transfer operation. The non-split read, write and pseudo
write transfer will set the SAM port into output mode or input mode. The split read and write transfers will not
change the SAM port mode set by preceding normal transfer operation. RAM port operation may be performed
independently except during split transfers. In the split register mode, serial data can be shifted in or out of one
of the split SAM registers starting from any at the 128 tap locations, excluding the last address of each split
SAM, data is shifted in or out sequentially starting from the selected tap location to the most significant bit (127
or 255) of the first split SAM and then the SAM pointer moves to the tap location selected for the second split
SAM to shift data in or out sequentially starting from this tap location to the most significant bit (255 or 127)
and finally wraps around to the least significant bit, as illustrated in the example below.
Tap location
----- HH-F-l-
Tap location
l ------ 11+
----- --f-irh-i-
REFRESH
The SAM data registers are static flip-flop, therefore a refresh is not required.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
TC528128B
DATA TRANSFER OPERATION
The TC528128B features two types of internal bidirectional data transfer capability between RAM and the
SAM, as shown in Figure 11. During a normal (Non-split) transfer, 256 words by 8 bits of data can be loaded
from RAM to SAM (Read Transfer) or from SAM to RAM (Write Transfer). During a split transfer. 128 words
by 8 bits of data can be loaded from the lower / upper half of the RAM into the lower/upper half of the SAM
(Split Read Transfer) or from the lower / upper half of the SAM into the lower/ upper half of the RAM (Split
Write Transfer). The normal transfer and split transfer modes are controlled by the DSF special function input
signal.
256 columns 128 columns 128 columns
w----"'-""""-
512x128x8 512x128x8
512 512x256x8 s12 Memory Memory
rows Memory Cell Array rows Cell Array Cell Array
256x8 (ctr 128x8 128x8 C',-ee-5
Figure 1 l. (a) Normal (Non-split) Transfer (b) Split Transfer
As shown in Table 5, the TC528128B supports five types of transfer operations: Read transfer, Split read
transfer, Write transfer, Split write transfer and Pseudo write transfer. Data transfer operations between RAM
and SAM are invoked by holding the Trr/o-E signal "low" at the falling edge of m. The type of data transfer
operation is determined by the state of m, w-B / WE E and DSF latched at the falling edge of m. During
normal (Non-split) data transfer operations, the SAM port is switched from input to output mode (Read transfer)
or output to input mode (Write transfer / Pseudo write transfer) whereas it remains unchanged during split
transfer operations (Split read or split write transfers). During a data transfer cycle, the row address Ao-Ae select
one of the 512 rows of the memory array to or from which data will be transferred and the column address Ao-A,
select one of the tap locations in the serial register. The selected tap location is the start position in the SAM port
from which the first serial data will be read out during the subsequent serial read cycle or the start position in
the SAM port into which the first serial data will be written during the subsequent serial write cycle. During split
data transfer cycles, the most significant column address (A7C) is controlled internally to determine which half
of the serial register will be reloaded from the RAM array.
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Table 5. Transfer Modes
at the falling edge of k-Eg
W - - - __ - Transfer Mode Transfer Direction Transfer Bit SAM Port Mode
CAS DT/OE WB/WE SE DSF
H L H * L Read Transfer RAM - SAM 256x8 Input - Output
H L L L L Write Transfer SAM --y RAM 256x8 Output - Input
H L L H L Pseudo Write Transfer - - Output - Input
H L H * H Split Read Transfer RAM --9 SAM 128x8 Not changed
H L L * H Split Write Transfer SAM - RAM 128x8 Not changed
* 2 "H" or "L''
READ TRANSFER CYCLE
A read transfer consists of loading a selected row of data from the RAM array into the SAM register. A
read transfer is invoked by holding ER "high", D-T/OE "low" WIT/WTI "high" and DSF "low" at the falling
edge of m. The row address selected at the falling edge of EM determines the RAM row to be transferred
into the SAM. The transfer cycle is completed at the rising edge of D-T/tTic. When the transfer is completed, the
SAM port is set into the output mode. In a read / real time read transfer cycle, the transfer of a new row of data
is completed at the rising edge of wr/o-E and this data becomes valid on the SIO lines after the specified access
time tSCA from the rising edge of the subsequent serial clock (SC)cycle. The start address of the serial pointer
of the SAM is determined by the column address selected at the falling edge of CTG.
Figure 12 shows the operation block diagram for read transfer operation.
SAM Start Address ON
T?????T ..................
....... 'rirt
lllllll /"
256 x 8bits
Ao-N Cy
'affW//////W//ff%fffffffW//W/t
l l l 14-"! 11
512x256x8 bits
Memory Cell Array
ciziity
Serial Read
- Selected Row
Figure 12. Block Diagram for Read Transfer Operation
In a read transfer cycle (which is preceded by a write transfer cycle), the SC clock must be held at a
constant VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur until
after the specified delay tTSD from the rising edge of D-T/O-E, as shown in Figure 13.
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T:7G /----ta-----1 -f"'-"--'"'-
Ag-Att '/ L, WSAM Start 'Zfff%%fgfff%f%h%%fh,
W/WE 'ft%Z%f8a E“ R%%%%fffff%%%%%%%gf%%ffff%%,
Ff/trg ggggEgggg2 4L / J lsaaa%%gatiaaf
DSF/ L Iaffff%%%fff%%%%%%%%%%f%ff%,
SC \ / i.' U hibit Ri i T iti l J L f l
i, n I 5 ng fans On: tr i' "sa' \
SK) . (EC:
Figure l3, Read Transfer Timing
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous row data
appears on the SIO lines until the Ft/UE signal goes "high" and the serial access time tSCA for the following
serial clock is satisfied. This feature allows for the first bit of the new row of data to appear on the serial output
as soon as the last bit of the previous row has been strobed without any timing loss. To make this continuous
data flow possible, the rising edge of 5W5]: must be synchronized with ITM, CAS and the subsequent rising
edge of SC (tRm, ICTH, and tTSL/tTSD must be satisfied), as shown in Figure 14.
The timing restriction tTSL/ tTSD are 5ns min / 15ns min. The split read transfer mode eliminates these
timing restrictions.
Ao-Att Row Address
Wg/WI? H
tmug L
SC trs=5ns trso=1ns
Slth--slth l x I x x t 1C x:
Previous Row Data -wi.-- New Row Data
Figure 14. Real Time Read Transfer
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WRITE TRANSFER CYCLE
A write transfer cycle consist of loading the content of the SAM register into a selected row of the RAM
array. If the SAM data to be transferred must first be loaded through the SAM port, a pseudo write transfer
operation must precede the write transfer cycles. However, if the SAM port data to be transferred into the RAM
was previously loaded into the SAM via a read transfer, the SAM to RAM transfer can be executed simply by
performing a write transfer directly. A write transfer is invoked by holding m "high", m/TE "low", w-B/W-E
"low", SE "low" and DSF "low" at the falling edge of RVs. This write transfer is selectively controlled per
RAM I/O block by setting the mask data on the Wi/IOi lines at the falling edge of EPT5 (same as in the write-
per-bit operation). Figure 15 and 16 show the timing diagram and block diagram for write transfer operations,
respectively.
A0~Aa mmm—WW
WEIWE 2WWWW) L %%%fffff%ffffffffffffffff%fff%ffffffffffffffffffffffffffffffh,
T/_E =W2ff4ef,) ic =WWWWWWaWWWWi
1Nollth-Nl8llth --aasiraii: .
Tii" ypj'f4'?effp'ft'rfgfel Tq%f%ffffffff%fffffff%%% 'i-ts-lui.'
SC _/ l / i', \ Inhibit Rising Transition \ /--c./--n,
SlorsSlth czitziriiiiirii)
DSF ,rffWafb%il L BMff%ffWgfffya%%%rfffgf%fffffffff%%gfffffff%2
Mask Data 0 : Not Transferred
t : Transferred
Figure 15. Write Transfer Timing
The row address selected at the falling edge of m determines the RAM row address into which the data
will be transferred. The column address selected at the falling edge of m determines the start address of the
serial pointer of the SAM. After the write transfer is completed, the SIO lines are set in the input mode so that
serial data synchronized with the SC clock can be loaded.
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SAM Start Address
???Wi'? ------------- f m
I-ii-f /,.1,-f------sii-c-ko Slth--SKh,
l I 1 I / SAM 1111
Air-Ae (l -ci, 256x8bits
i ' //////////////////////////////////// pr- SRelected
t LCC, 512x256x8bits W
a: _ Memory Cell Array
W1/IO1 Wa/ tth W3/103 Wa/ kh Ws/Os Ws/ IOs Wr/ IO) Wtitlth
W] I /////// INlffft //////// WM d “m
Mask "I'' "i" "ti'' "I'' "I" "i'' ugl "I"
Transfer operation
is inhibited.
Transfer operation
is inhibited.
Figure 16. Block Diagram for Write Transfer Operation
When consecutive write transfer operations are performed, new data must not be written into the serial
register until the m cycle of the preceding write transfer is completed. Consequently, the SC clock must be
held at a constant Va, or VlH during the m cycle. A rising edge of the SC Clock is only allowed after the
specified delay tSRD from the rising edge of m, at which time a new row of data can be written in the serial
register.
PSEUDO WRITE TRANSFER CYCLE
A pseudo write transfer cycle must be performed before loading data into the serial register after a read
transfer operation has been executed. The only purpose of a pseudo write transfer is to change the SAM port
mode from output mode to input mode (A data transfer from SAM to RAM does not occur). After the serial
register is loaded with new data, a write transfer cycle must be performed to transfer the data from SAM to
RAM. A pseudo write transfer is invoked by holding CTG" "high", Cyt/O-E" "low", w-B/W-E "low", E "high"
and DSF "low" at the falling edge of R—AS. The timing conditions are the same as the one for the write transfer
cycle except for the state of s-E at the falling edge of R73.
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SPLIT DATA TRANSFER AND QSF
The TC528128B features a bi-directional split data transfer capability between the RAM and the SAM.
During split data transfer operation, the serial register is split into two halves which can be controlled
independently. Split read or split write transfer operations can be performed to or from one half of the serial
register while serial data can be shifted into or out of the other half of the serial register, as shown in Figure 17.
The most significant column address location (A7C) is controlled internally to determines which half of the
serial register will be reloaded from the RAM array. QSF is an output in which indicates which half of the serial
register is in an active state. QSF changes state when the last SC clock is applied to active split SAM, as shown
in Figure 18.
128 columns 128 columns
w---------"-
512 Active SAM QSF Level
rows '%fff//////dy//, "
lower SAM "Low
upper SAM "High"
[131; §§ij 128 ha
Active Non-Active
Figure 17. Split Register Mode
Last SC First SC Last SC First sc
(127) (255)
sc-u-Lf-dl-lil/L''-'-?, ------.--..--_- _r--l,ri,liil/r'.ir-"n1
't "high" 't
osr "low" I I "low"
lower SAM 2 Active upper SAM : Active lower SAM : Active
Figure 18. QSF Output State During Split Register Mode
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SPLIT READ TRANSFER CYCLE
A split read transfer consists of loading127 words by 8 bits of data from a selected row of the split RAM
array into the corresponding non-active split SAM register.
Serial data can be shifted out of the other half of the split SAM register simultaneously. The block diagram
and timing diagram for split read transfer mode are shown in Figure 19 and 20, respectively. During split read
transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
eliminating timing restrictions as in the case of on-the-fly read transfers. A split read transfer can be performed
after a delay of tsrs, from the change of state of the QSF output, is satisfied.
'afy//fW,
A''''" 'f''", r
I Active 1
’llllllllJl/Ill
L°\;.J
Figure 19. Block Diagram for Split Read Transfer
AM. izazacd.w Xiiiia SAM Start '%fffff5%f%ff%%'fff%f%%Wt
. H Ao-As .
wmw: awww?
Isms 'iCt2"8Wz%il L
as: t;
i-tm.- i n E‘Jnd":
QSF l l", I
Figure 20. Timing Diagram for Split Read Transfer
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A normal (Non-split) read transfer operation must precede split read transfer cycles as shown in the
example in Figure 21.
Tran>fer/\15plit Read Transfer J' Read Transfer
"iii''''"':');?'" "t? j''"))'"
Figure 21. Example of Consecutive Read Transfer Operations
SPLIT WRITE TRANSFER CYCLE
A split write transfer consists of loading 128 words by 8 bits of data from the non-active split SAM register
into a selected row of the corresponding split RAM array.
Serial data can be shifted into the other half of the split SAM register simultaneously. The block diagram
and timing diagram for split write transfer mode are shown in Figure 22 and 23, respectively. During split write
transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus
allowing for real time transfer. A split write transfer can be performed after a delay of tsrs, from the change of
state of the QSF output, is satisfied.
7 ///////////,
l, I 17/ [1/7777/7/
1,,,ty,,sg,t,, b'
g"''''
Figure 22. Block Diagram for Split Write Transfer
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Ao-N, 2EaEfElrUaviirNEECTiaiu-strrClP,
WE/WE 'eggT4ftrgWl L
57/07 'gWEEWkl. L Tffff%ff%%fff%f%f%%%%f%%%f%%ff%fff'p,
DSF 2WWfW?9 i' '%%fff%ffffff%%%f%f%fff%ff%%ffff%fg%%r),
W1/IO1~W3/|Oa -------CEEstEiiD .
s-tass, T i' '.uts.r.s; TH ..'
05F T" ' ",',, L
Figure 23. Timing Diagram for Split Write Transfer
A pseudo write transfer operation must precede split transfer cycles as shown in the example in Figure 24.
The purpose of the pseudo write transfer operation is to switch the SAM port from output mode to input mode
and to set the initial tap location prior to split write transfer operations.
Pseudo Write Transfer y,,,""""""";";"''"'''';- Transfer /""'"'"rci'i"writ.e Transfer w''''"'''"'""''"
EAT L14 / . \I‘J f UH /
SC ............................ .', ... ..................................... .-. ................... I ..................... . ................
ei-ij/m'',:')::)-':',,,')'::')::";;)')::;
i) t t t I) t
Figure 24. Example of consecutive Write Transfer Operations
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SPLIT-REGISTER OPERATION SEQUENCE (EXAMPLE)
Split read / write transfers must be preceded by a normal (Non-split) transfer such as a read, write or
pseudo write transfer. Figure 25 illustrates an example of split register operation sequence after device power-
up and initialization. After power-up, a minimum of 8 k-h-s and 8 SC clock cycles must be performed to properly
initialize the device. A read transfer is then performed and the column address latched at the falling edge of m
sets the SAM tap pointer location which up to that point was in an undefined location. Subsequently, the pointer
address is incremented by cycling the serial clock SC from the starting location to the last location in the register
(address 255) and wraps around to the tap location set by the split read transfer performed for the lower SAM
while the upper SAM is being accessed. The SAM address is incremented as long as SC is clocked. The
following split read transfer sets a new tap location in the upper split SAM register address 127 in this example
and the pointer is incremented from this location by cycling the SC clock.
Ptairtter
pause Dummy
t2tlhal Cycle
r_A_V_A_‘
Transfer
Split Read
Transfer
Split Read
Transfer
j. serugoutpuii'.,i. ,'. i.' Serial
i E i . Input
' . i i i I
J?..e.ti.c..e.s..0.l ii z s ' .
" P................ '. . iUpper i iUpper i
iSAM i. ISAM i Upper
........... i 3 g SAM
........... ..." Desricest21 h' L i i., m." w".:' ttesettsetSAh/ Att',".
Reset/SetSAM i Sm" '.. painter 'ss ..-"'
t , ..
pointer
_ Pointer Location I
Undefined
Figure 25. Example of Split SAM Registers Operation Sequence
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The next operation is a pseudo write transfer which switches the SAM port from output mode to input
mode in preparation for either write transfers or split write transfers. The column address latched at the falling
edge of C-Aff during the pseudo write transfer sets the serial register tap location. Serial data will be written into
the SAM starting from this location.
TRANSFER OPERATION WITHOUT CAS
During all transfer Cycles, the tTM input clock must be cycled. so that the column address are latched at
the falling edge of CM, to set the SAM tap location. If CAS was maintained at a constant "high" level during
a transfer cycle, the SAM pointer location would be undefined. Therefore a transfer cycle with tas held "high"
is not allowed (Refer to the illustration below).
R73 -""'-''"-'-"-7 C---""'''"""-
Proper
m l / Transfer
Address WROW EiiiiX SAM Start ZgWWWWWl
EAT -'"'-'"""1 f--
m It,,,,,,,,
Address 2=aa?CCitia=aggEaali=Ea==gi'
TAP LOCATION SELECTION IN SPLIT TRANSFER OPERATION
(a) In a split transfer operation, column addresses AOC through A6C must be latched at the falling edge of
CAS in order to set the tap location in one of the split SAM registers. During a split transfer. column
address A7C is controlled internally and therefore it is ignored internally at the falling edge of CAS.
RES —\ f-'''""--
CAT l ______}
Addresses 2igEagE2 Row MEBr Tap address (WWEWffgggfgZ=fifffgfffi
AOR--A8R AOC~A6C (A7C is don't care:High or Low)
During a split transfer, it is not allowed to set the last address location (AOC-A6C=7F), in either the
lower SAM or the upper SAM, as the tap location.
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(b) In the case of multiple split transfers performed into the same split SAM register, the tap location
specified during the last split transfer, before QSF toggles, will prevail. In the example shown below,
multiple split transfers are performed into the upper SAM (Non-active) while the lower SAM (active)
is being accessed at the time when QSF toggles, the first SC serial clock will start shifting serial data
starting from the Tap N address location.
m --'"''l sr""'-"'-) rsh-sc-_-r---'--------
Address --lttow 1 )(Tasc0---0tew 2tao 2)--%--Oow NXTapE
lower SAM : Active
QSF upper SAM : Non-active " '7 lower SAM : Non-active
I Last First upper SAM : Active
t Cloclg Clock
SC m ---....-- SS ------- f'"llLr1,..tCb'',f
Multiple Split transfer into upper SAM
Serial access of lower SAM
Serial access of upper SAM
starting at Tap N location
SPLIT READ / WRITE TRANSFER OPERATION ALLOWABLE PERIOD
Figure 26 illustrates the relationship between the serial clock SC and the special function output QSF
during split read / write transfers and highlights the time periods where split transfers are allowed, relative to SC
and QSF.
Last First Last First Last First
Clock Clock Clock Clock Clock Clock
SC -rll] I I 'f, J‘\‘ I I I I I T, I‘\\ I f I I
"s _ _
tsw tsrs tso, tsrs tsm tsvs
Split -. rlvr “If' e "T'" -
Read/Write V -, r ‘
Transfer YES a NO ' _ YES ff NO r -m YES NO YES
allowed.
Figure 26. Split Transfer Operation Allowable Periods
As indicated in Figure 26, a split read / write transfer is not allowed during the period of 15TH + ISTS.
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SPLIT TRANSFER CYCLE AFTER NORMAL TRANSFER CYCLE
A split transfer may be performed following a normal transfer (Read / Write / Pseudo-Write transfer)
provided that a minimum delay of 30ns from the rising edge of the first clock SC is satisfied (Refer to the
illustration shown below).
Next TransfeLEL
Not Allowed 'f
Next Transfer Operation is allowed.
m -""--u._._/ a A-r--"'-
m "u-l I \_r
6176? -n r '',, "su.-,-;""-"'"'-"""
DSF f m
QSF , l
sc 5 f'1f"LrLf1f1.f1.f1 --..-----
Transfer Ogeration E 30ns:
NORMAL READ TRANSFER CYCLE AFTER NORMAL READ TRANSFER
Another read transfer may be performed following the read transfer provided that a minimum delay of
30ns from the rising edge of the first clock SC is satisfied (Refer to the illustration shown below).
m -'"--""""1-.----..--/r,' "s-f-"-
EA? -------u..v-,', \__/
I5ttt5t \ / i J
t2SF VA;
sc l, CLrLrLrLrL.rLrl ....-----.
Transfer Ogeration E30nsi
Next Transfer :
-. fi ‘ T . .
Not Allowed ', Next ransfer Operation " allow
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NORMAL TRANSFER AFTER SPLIT TRANSFER
A normal transfer (read / write / pseudo write) may be performed following split transfer operation
provided that a 30ns minimun delay is satisfied after the QSF signal toggles.
Split Transfer... I 30ns Min.
_---Norrnal Transfer Operation Allowed
POWER-UP
Power must be applied to the "ITA-ff and DT/UE input signals to pull them "high" before or at the same time
as the Vcc supply is turned on. After power-up, a pause of 200 “seconds minimum is required with m and
D-T/O-E' held "high". After the pause, a minimum of 8 m and 8 SC dummy cycles must be performed to
stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization
period, the D-T/O-E signal must be held "high". If the internal refresh counter is used, a minimum 8 C-AS-before-
ITA-g initialization cycles are required instead of 8 RTS cycles.
INITIAL STATE AFTER POWER-UP
When power is achieved with "it-hrs. tTAR, DT/OE and 'y-B/ur-E held "high", the internal state of the
TC528128B is automatically set as follows.
However, the initial state can not be guaranteed for various power-up conditions and input signal levels.
Therefore, it is recommended that the initial state be set after the initialization of the device is performed (200
'tseconds pause followed by a minimum of 8 m cycles and 8 SC cycles) and before valid operations begin,
State after power-up
SAM pon Input Mode
QSF High-lmpedance
Color Register all "O''
WMI Register Write Enable
TAP pointer Invalid
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