TC514400ZL-80 ,80 ns, 4-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC=5V110%, Ta=0~70°C)
5mm. PARAMETER
Operating Current
ICCl Avera ..
TC514402ASJ-80 ,80 ns, 4-bit generation dynamic RAM1048,576 WORD x 4 BIT DYNAMIC RAM
DESCRIPTION
The TC514402AP/AJ/ASJ/AZ is the new generation ..
TC514402AZ-60 ,60 ns, 4-bit generation dynamic RAMfeatures include single power supply of 5Vi10% tolerance,
the TC514402AP/AJ/ASJ/AT to be package ..
TC514402AZ-70 ,70 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576
word by 4 bit organization
. Fast access time and cycle time
TC51440 ..
TC514402AZ-80 ,80 ns, 4-bit generation dynamic RAMBLOCK DIAGRAM
WMO1 WMO2 WMOJ WUIOI
O O 0 C)
COLUMN
DECODEI
SENSE AMP.
IIO GATE
MEMORY
..
TC514410ASJ-60 ,60 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization
I Fast access time and cycle time
. Single
..
TC7WG125FK ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTStart of commercial production 2006-021 2014-03-01 ..
TC7WG126FC , CMOS Digital Integrated Circuit Silicon Monolithic Dual Bus Buffer with 3-STATE Output
TC7WG126FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-021 2014-03-01 T ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC7WG14FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4. ..
TC7WG17FK ,L-MOS LVP seriesabsolute maximum ratings. OUT Start of commercial production2006-02Note 3: V < GND OUT1 2014-03-01 ..
TC514400ZL-80
100 ns, 4-bit generation dynamic RAM
* ,. . . . . .
1,048,575 UORDX 4 BIT DYNAMIC RAN This IS advanced 1nform§tlon and '.specifica"cms
are subject to change without notlce.
DESCRIPTION
The TC51p00JL/2L is the new generation dynamic RAN organized 1,048,576 words by 4 bits.
The TCSlAhOOJL/ZL utilizes TOSHIBA'S CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the
system user. Multiplexed address Inputs permit the TC514h00JL/ZL to be packaged in a
standard 26/20 pin plastic SOJ and 20 pin plastic ZIP. The'package size provides high
system bit densities and is compatible with widely available automated testing and inser-
tion equipment. System oriented features include single power supply of 5V:10% tolerance,
direct interfacing capability with high performance logic families such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 578aH MAX. Operating(TCSlé400JL/ZL-80)
TC514400Jur2L-8M-10 4953M MAX. operat:ing(Tc51000JL/zL-10)
ERAC ITA-T; Access Time 80ns lOOns 2.2mw MAX. Standby
Column Address . Out:puts unlatched at cycle end allows
tAA Access Time tions 50ns two-dimensional chy3Lselet:tioe
CCAC tTig Access Time 20ns 25ns . RteyHodify-vrite, CAS before RAS refresh,
CRC Cycle Time Lions 180ns RAS-only refresh, Iit.iftn refresh and
Fast Pa e Mode Fast Page Mode capability
tPc Cycle Time 50ns 60ns . All inputs and outputs TTL compatible
. 1024 refresh cycles/128ms
. Single power supply of 5V2102 with a . Package Plastic SOJ: TC514400JL
built-in VBB generator Plastic ZIP: TC51li4002L
l "V “ti
ple CONNECTIUu BLOCK DIGARAM 1/011/021/03I/04
Plastic SOJ Plastic ZIP
---~ v y
oi: _1::- r . (27's; CC " 4 4
[/03 r J .3:
'ii l. - 1/04 mu IN DATA our 15T;
Irss ste,'' LiCvol surrzns BUFFERS
'e-i) 35' CE, WRITE WR""----?' l 4 , l
A0 'tf,, {1:6 A9 I
...‘ tr5 Al - N .2 CLOCK _
A2 53;: 3% A3 t-5rscr--iflil'rAtt'lit' -
V09 1-: {rm 1 ,
A5 .11: 5:5” _ COLUMN A COLUMN
A7 'JY: tld? Aoo-c 10 ADDRESS 10) usconm
- Pill, A8 AI o-- BUFFERSUO) -V
A2 J SENSE AMP.
PIN NAMES A3 o-- 'lg%'ii'ifaa, LA) GATE
'ser? Address Inputs A4c i -wer./
RAS Row Address Strobe Al"-- REFRESH x4 l
cts Column Address Strobe Alio-- [iii))'),':?''':'?" iii MauORY
' . Mo-- l now _ " ' '
XOEITE Read/erte Input A8 ADDRESS 10) iii,'?,; 1t)24 ARRAY
E Output Enable A9 c: 1 uvrrsasOo) v E, ' 1024x1024x4
1/01'uI/olt Data Input/Output N l loc,,
Vcc Power (+5il) 'Tis-ics-CIA/dy/ill I SUBSTRATE BIAS
VSS Ground GENERATOR
TC51 440NLZL-8o
TC51 440NLZL--1 o
ABSOLUTE MAX IMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage VIN -IN 7 V 1
Output Voltage ilogT -1~7 v 1
Power Supply Voltage Vcc -1'\' 7 V 1
Operating Temperature TOPR O'u70 "c 1
Storage Temperature TSTG -55~150 "c 1
Soldering Temperature . Time TSOLDER MP . 10 °C-sec 1
Power Dissipation PD 600 . mil 1
Short Circuit Output Current Iotrr 50 mA 1
RECOf-iMENDED DC OPERATING CONDITIONS (Tam0s70''C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE
VCC Supply Voltage 4.5 5.0 5.5 V 2
VIH Input High Voltage 2.6 - 6.5 V 2
VII. Input Low Voltage -1.0 - 0.8 V 2
DC ELECTRICAL CHARACTERISTICS (vctr5vt10T, Ta=0'u70''C)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
Operating Current TC514400Juw2L-80 - 105
ICCl AE.tE.agt2tser Supply Operating Current mA 3,4,5
(ms, CAS, Address Cycling: tRC"tRC MIN.) TCSIHOOJWHO - 90
Standby Current
ICCZ Power Supply Standby Current - 2 mA
tEiG=t7G=i)
torg' Only Refresh Current - TC5t440tubi-80 - 105
ICC3 Ieytre Power Su_pply Current, RAS Only Mode mA 3,5
(RAS Cycling, CAS-VIH: CRC"tRC MIN.) TC514400JUr2L-10 - 90
Fast Page Made Current TC5t440tUV2L-80 - 7O
ICC4 Average Power Supply Current, Fast Page Mode mA 3,4,5
(msvn, 6Wi, Address Cycling: cpc-cpc MIN.) TC5i4400JV2L-i0 - 60
I Standby Current
Pow 1 nt -
ccs '?l'fae-fyl?di-t'f.'2"v'f'y Curte 400 "
triis%setozTsm Refresh Current TC51440tu1.i-80 - 105
IGC6 Average Power Supply Current, irig Before m m 3
Mode GM, Encycung: tRC"tRC MIN.) Tcsmoon/ZL-Io - 90
Battery Back Up Current
Average Power Supply Current, Battery Back Up Node
ICC7 (i5iGU57G Before rt7G Cycling or 0.2V, mvcc-OJV. Mvcc- - 500 uA 3,6
0.2V, A0'u9"1lCc-0.211 or 0.2ll, T/01'uh"Vcc-0.2v,
0.2V or OPEN: tRCIIZSHS, tms'tms MIN. Nlps)
Input Leakage Current
110..) Input Leakage Current, any Input -10 10 "
(OVSVINS 6.5V, All Other Pins Not Under Test-OV)
Out ut Leaka e Current _
100-) (D031- is disgbled, ovzvom: 5.5V) -10 IO "
Iltm Output 11¢:er 2 4 - V
Output H Level Voltage (Tours-Smit) .
VOL 83:53: 1,;t1/eleve1 Voltage (Iour=4.2mA) - 0.li V
TC51 44oNLML-8o
TC51 440NLlZL-1 O ,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS
(Vcc-5V11OZ, Taxs0'v70''C)(Noees 7, 8, 9)
TC514400J‘L/ TC514400JL/
SYMBOL PARAMETER ZL-BO ZL-1O UNIT NOTES
MIN. _ MAX. MIN. MAX.
tRc Random Read or write Cycle Time 150 - ' 180 - ns
tp§nq Read-Modify-Vie Cycle Time 205 - 245 - ns
tPC Fast Page Mode Cycle Time 50 .. 60 - ns
Fast Page Mode Read-Modify-Write Cycle
t?RMW Time 105 - 125 - ns
tRAC Access Time from "tws- - 80 - 100 ns 101546
tCAC Access Time from 25E - 20 - 25 ns 10,15
tAA Access Time from Column Address - 40 - 50 ns 10,16
tCPA Aecess Time from tTiig Precharge - 45 - 55 ns 10
ten EST to Output in Low-Z 0 - . 0 - ns 10
{OFF Output Buffer Turn-off Delay 0 20 O 20 ns 11
" Transition Time (Rise and Fall) 3 50 3 50 ns 9
tny R-Ag Precharge Time 60 - 70 - ns
tug RTs Pulse Width 80 10,000 100 10,000 ns
tRASP EK§ Pulse Width (Fast Page Mode) 80 200,000 100 200,000 ns
tnsn Tii';- Hold Time 20 - 25 - ns
tcsu Trig Hold Time 80 - 100 - ns
CRHcp E_§ Precharge to iigTii Hold Time 45 - 55 - ns
tCAS Ts Pulse Width 20 10,000 25 10,000 as
tRCD i]: to iuts Delay Time 20 60 25 75 ns 15
tRAD "tWi" to Column Address Delay Time 15 40 20 50 ns 16
ttRP tTirii to ti-i?, Precharge Time 5 ... 10 - ns
tCP "triCs Precharge Time 10 - 10 - ns
tASR Row Address Set-Up Time 0 - O - n3
CRAY Row Address Hold Time 10 - 15 - ns
tASC Column Address Set-Up Time 0 - 0 - ns
tCAH Column Address Hold Time 15 - 20 - ns
Column Address Hold Time referenced to
tAR rtiiT 60 - 75 - ns
tRAJ. Column Address to XM Lead Time " - 50 - ns
tttcs Read Command Set-Up Time 0 - 0 - ns
tRCH Read Command Hold Time t) - 0 - ns 12
TC51 4400J LlzL-80
TC51 440NLML--1 O
ELECTRICAL CHARACTERISTICS AND REc0Nl4EN0E0 M OPERATING CONDITIONS (Continued)
Ic514400JL/ TCSIMOOJL/
SYMBOL PARAMETER ZL-80 2L-10 UNITS NOTES
MIN. MAX. MIN. MAX.
CRRH Read Command Hold Time referenced to m 0 - 0 - ns 12
twen Write Command Bold Time 15 C" 20 - ns
CWCR Write Command Bold Time referenced to RKS 60 - . 75 - ns
twp Write Command Pulse Width 15 - 20 - ns
ERWL Write Command to as Lead Time 20 - 25 - ns
tam. Write Command to "t5ii5 Lead Time 20 - 25 - ns
EDS Data Set-Up Time 0 - 0 - ns 13
tpa Data Bold Time 15 - 20 - ns 13
tDHR Data Hold Time referenced to m 60 - 75 - ns
CREF Refresh Period - 128 - 128 ms
t5wcs Write Command Set-Op Time 0 - O - ns 14
CCND CET; to WIT: Delay Time 50 " 60 - ns 14
mm Wig to i7rtrfX Delay Time 110 - 135 - ns 14
CAWD Column Address to Tik-trg Delay Time 70 - 85 - ns 14
(TA? Precharge to TIR-IN Delay Time
ECPWD (Fast Page Mode) 75 - 90 - ns 14
tCSR Tyirg Set-Up Time (CE before 'Eirg Cycle) 5 - 5 - ns
item C73 Hold Time ((TS' before EB" Cycle) 15 - 20 - ns
ERPC W5 to c7t"g Precharge Time 0 - 0 - ns
ECPT cra- Precharge Time 40 - 50 - as
(m before TOG" Counter Test Cycle)
eittm m Hold Time referenced to 6E q 10 - 20 - ns
tOEA " Access Time - 20 - 25 ns
toi-EI) 6? to Data Delay 20 - 25 - ns
ttm: Output Buffer Turn Off Delay Time from 5E 0 20 O 20 ns 11
tom 'trt:" Command Hold Time 20 - 25 - ns
Cuts Write Command Set-op Time (Test Mode In) 10 - 10 - ns
tum Write Command Hold Time (Test Node In) 10 - 10 - ns
tNR? 'ft-rg-Ed/rue-rl-sf/tul?,,'')' Time IO - 10 - ns
WRITE to RAS Hold Time _
{HRH ttTris- before Ttri" Cycle) 10 - 10 - ns
TC51 4400J L)ZL-80
TC51 44000 L/EL-l o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE TEST MODE
TC514400JL/ TC51ti400JL/
SYMBOL PARAMETER ZL-80 ZL-10 - UNIT NOTES
MIN. MAX. MIN. MAX.
tRC Random Read or Write Cycle Time 155 - 185 - ns
tPC Fast Page Mode Cycle Time 55 - .65 - ns
time Access Time from Tair - 85 - 105 ns 10.15.16
tCAC Access Time from EX§' - 25 - 30 as 10,15
tAA Access Time from Column Address - 45 - 55 ns 10,16
tCPA Access Time from tTre Precharge - 50 - 60 ns
tRAS "R-ii-fi" Pulse Width 85 10,000 105 10,000 as
tRASP 1iiCs" Pulse Width(Fast Page Mode) 85 200,000 105 200,000 ns
tRsu iii Hold Time 25 - 30 - ns
tam cts Hold Time 85 - 105 - ns
tRHCP C73 Precharge to "rA'"i'j' Hold Time 50 - 60 - ns
tCAS ETii Pulse Width 25 10,000 30 10,000 as
cm Column Address to "iiii-i; Lead Time 45 - 55 - ns
CAPACITANCE (VCC=5V:102, f=1MHz, Ta¢0~70°C)
SYMB 0L PARAMETER MIN . MAX . UNIT
CII Input Capacitance oui-A9) - S pF
C12 Input Capacitance tits, m, TititW, 6?) . - 7 pF
co Input/Output Capacitance (I/Ol'vI/OA) - 7 PF
TC51440NLML--80
TC51440NLlzL--10
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause per-
manent damage to the device.
2. A11 voltages are referenced to Ilss.
3. 1cc1, ICC3. Icon ICC6, ICC7 depend on cycle rate.
ti. Icc1, Icc4 depend on output loading. Specified value are obtained with the output
'5. Column address can be changed once or less while Errvrr, and EKE-VIH.
6, tRAs(max.)=IUS ls only ap'p11ed to refresh of battery-back up. tRAs(max.)-10us is
applied to functional operating.
7. An initial pause of 200us Is required after power-up followed by 8 fiET only refresh
cycles before proper device operation ls achieved. In case of using Internal
refresh counter, a minimum of 8 txg'before EETrerresh cycles Instead of 8
RAS only refresh cycles are required.
8. AC measurements assume tT=Sns.
9. VIH(min.) and VIL(max.) are refere'nce levels for measuring timing of input signals.
Also, transition times are measured between VIH and VIL.
IO, Measured with a load equivalent to 2 TTL loads and lOOpF.
ll. topp(max.) and tOEZ(max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
12. Either tRCH or tRRH must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles and to
WRITE leading edge in read-modify-write cycles.
14. tugs, tttND, tCHD, tAWD and tcpwn are not restrictive operating parameters. They
are included in the data sheet as electrical characteristics only. If wcst twcs
(min.) the cycle Is an early write cycle and data out pin will remain open circuit
(high Impedance) through the entire cycle; If tawni tpr(m1n.), tooit tcwp(min.),
tAND-k tAUD(min.) and tcmz tcmmin.) (Fast Page Node), the cycle " a read-
modify-write cycle and data out will contain data read from the selected cell: If
neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
Operation within the tRCD(max.) limit Insures that tRAC(max.) can be met.
tRCD(max.) is specified as a reference point only: If tRCD Is greater than the
specified tch(max.) limit, then access time is controlled by tCAC.
Operation within the tRAD(max.) limit Insures that tRAc(max.) can be met.
tRAD(max.) is specified as a reference point only: If CRAB ls greater than the
specified tRAD(max.) limit, then access time is controlled by tAA.
TC51 440NLdZL-80
TC51 440NLZL-1 o
READ CYCLE t
Irn, - 'r
tasa ‘m
A0--A9 IH
WRITE m
--- VIH -
L/Ol~I/0-l vor:
VALID DATA- our
vol, -
-: "il" or "L"
WRITE CYCLE (EARLY WRITE)
is m -
muss vm -
Vii, -
----- ll H -
wnrrs I --.
Tii:" Prrt -
Von~voa VI“ -
VALID DATA- IN
V1 L -
TC51 4400J L2L--8o
TC51 440NL2L--1 tl
WRITE CYCLE.(6§ CONTROLLED WRITE)
.__ V -
VII. -
1rm - u
VIL - ADD ass
WRITE IH
- VIH -
VIL ---
1/01~1/o4 m VALID DATA- IN
Vii, -
t "H" or "L"
READ-MODIFY-WRITE CYCLE
CAS IH
vii.--
A0149 m
VII,--
---- V -
wan: m
VIL---
VI/CH-
I/OH- V0" VI/OL -
TC51 4400d L)ZL-80
TC51 440NLML-1 0
FAST PAGE MODE READ CYCLE
V11. -
- VIH -
V1 L -
A0-A9 m
Ytt, -
warn: m
_ VIH -
VII. ---
tor? tCAC
'onz C
1/01~1/04 OH
VALID ' . " n " "
DATA-OUT 1 (/A . ll " L
FAST PAGE MODE WRITE CYCLE DATA-OUT 2
t RP men
'iirs" VI" -
vii.--- tCSH
tas IAS ASC tCAH
loss, IH 2
VII. -
----- y -
wan}: m
vit,--
Ytt,-.
1/01~x/04 IH
Vit, -
TC51 4400J LML-80
TC51 440NLlZL-.1 o
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
I/Ol~I/0-I
. II” I "H" or "L"
RAS ONLY REFRESH CYCLE
TC51 4400J LlzL--80
TC51 4400JUzL-1 o _
---- vm -
Ffff7) now
10-A9 v ADDRESS
X/////////////////////////////////////[[)(
Note: WRITE, tTiF"il" or " "
CAS BEFORE RAS REFRESH CYCLE
l "B" OT "L"
VIH - -
RAS y 41/ tRPC
vu, ----..V
/fff/ff///////))fffff)/////////
vm--, "
WRITE fffffféiéffvf
v0H - --t
I/O 1~I/04
VOL _-..-.-.....,..-,..)
Note.. TE, A0sA9="B" or " "
"lylillllllhll0l0llilylllllll[filllllfj,
l "H" Of "L"
TC51 4400J L/ZL-80
TC51440NL/zL-1 0
HIDDEN REFRESH CYCLE (READ)
11::“Kf tAR z l 'tRAS I...,
VIH - wry; tRCD - tnsn tam tear
m - 'mn 's)
t 17/04 fl/v, W 'ii')''''""-,?,??,,,?),,?"-"""""""""
VZZWZM IAA 'tif 'igEjEfgfifffffff%jff
:i: 102A (pp"ipppp"pj"pp'pp,
-t.2c-,l I torr'
I/01~I./0~1 vt,:.-..'..-----------------) VALID DATA-OUT
t "H" or "L"
TC51 4400J L2L-80
TC51440NLML-10 b
HIDDEN REFRESH CYCLE (WRITE)
tc'zRc'c'zzc 'd_.
tRCD ‘RSH leap
VIH - - - term
CAS / t ii) r
VII. -
A9 1:: :W Yit" iggggsz Is?,rrm?"iljf"""-
WRITil X: :W/% twp oi; (iiti,y,c/,o,sy/,/,,///o),/,jy/-),,
BT: t -Wpllllulillij1lllllilNljyilllllillliliilllllllyilllullilllllL,
L"01i04 :: I 1jj.lll2r "L,, oadl,, "1)llllllllllylfl%0llluliM00lliih,
-: "H" or "L"
TC51 4400J LML-80
TC51 440NLlzL--1 o
Tics BEFORE RAS REFRESH COUNTER TEST CYCLE
-irig VIH --
Vii, -
- VIH -
V11. -
A0-A9 COLUMN
V11. - ADDRESS
READ CYCLE t
RCS CAC
---- V -
WRITE IH
vii, -
- Vm -
Vit, -
I/Ol~1/04 VALID DATA-OUT
WRITE CYCLE "cm,
-.---- v - ‘wcu
mun: m
or: IH
Vit, -
Ins IDH
1/01~r/04 VALID DATA- IN
V11. -
tmtp tAWD
REAIFH00rFY-HRrTE CYCLE
--_ y -
want. IH ICAC
- V[H_ tom
or: 1021)
vu,---
losz tDS ‘DH
V01~X/O4 I/OH VALID
VI/OL---- DATA-IN
7h, , "ti" or "L" . VALID mm-our
TC51 440NLlzL-80
TC51 4400J LML--1 0 .
tRAS / L
r--"'----"))))))))))):),
. W 1llRlllllljlllllllllllhlllllllh,
7: "H" or "L"
TC51 44ONLML--8o
TC51 440NLdZL--1 0
READ CYCLE IN THE TEST MODE
A0-A9 Irm
---_ y
WHITE m
I/Ol~I/o4 v05 VALID mm-our
Yor, - l cm
Note: "tfry. "L" 7/], t "B" or "L"
“RITE CYCLE (EARLY WRITE) IN THE TEST MODE
--- y -
as 1rm -
If --.
m~49 tH
VII. ..--
WRITE vm -
Vtt, -
OE v1“
It,"-"""
i tDHit
'ps ' mu
VIH - -"-"""-='
I/OH/m V11, - ---------ium" tUra-tiii---------------- OPEN
TC51 4400J L/ZL--80
TC51 440NLML-1 0
FAST PAGE MODE READ CYCLE IN THE TEST MODE
Yrt, -
A0 " vm
Ytt,--
---- If
WRITE m
Yrt,---
L/Dt-tpt" OH
ALID -
mm-our 1 v m DATA our 2
Note: 0iT--"i." '= "tt" or "L"
FAST PAGE MODE WRITE CYCLE (EARLY WRITE) IN THE TEST MODE
- V - t
tRCD t s
VIL - t
VIH - tw
man's y -
55 3?; I ""rll/illl,yi,yiilif"lll,j11lll-"-l-l2lll,_lllllllllllillli
Ins t ,
Itns L‘DH [ DH, t
v - VALID y D v D
I/Oht/O‘ Vi: - DATA-IN 1 Af-Im 2 Pale N
TC51 4400JL/ZL-80
TC51 440NLML-1 o
TEST MODE
The TC514é00JL/ZL ls the RAN organized 1,068,576 words by 4 bits, it Is internally
organized 524,288 words by 8 bits. In "Test Node", Kata are written into 8 sectors in
parallel and retrieved the same way. ADC is not used. If, upon reading, two bits on
one 1/0 pin are equal (all "I"s or "0"s), the I/O pin indicates a "1".
If they were not equal, the I/O pin would indicate a "0". Fig. 1 shows the block
diagram of TCSIAAOOJL/ZL. In "Test Node", the lMx 4 DRAM can be tested as if it ware
a SIZKX 4 DRAM.
"Wiffi, CK§'Before Erg Refresh Cycle" puts the device into "Test Mode". And "C33 Before
'rt7ig Refresh Cycle" or 'ruiT; Only Refresh Cycle" puts it back intoiVNbrmal Node". In the
Test Mode, "imrrir, TiT Before Eiig Refresh Cycle" performs the refresh operation with
the interhal refresh address counter. The "Test Mode" function reduces test times (1/2
in case of N test patterns).
TC51 4400J LZL-80
TC51 440NLML--1 0 .
BLOCK DIAGRAM IN THE TEST MODE
Mc VCC
o I Normal
AOC A , .
Normal -osGF--- 512K block "-9 Test.
1/01 -'so, -- V01
Test AOC - B
--
r, JD-CUC-,
----o I Normal
----dp: Vcc
: I Normal
Aoc I k c ,
Normal r'-''--?-- 512K b oc Ey-----;..:"?
o-- T: ’4 Test
1/02 -e2. - 1/02
Test AOC D
c15 "'lD-----tcc,
-.-o Normal
L-----.-
-.-..-...doc V c
t---o Normal
Normal T--o---- E Test
1/03 --o _ 1/03
Test Aoc: F
-0sso----- 512K blotk , Te"
? --,1lD-------1C2Li
--o I Normll
1/04 -oso,
Test L AOC H T t
o I Normal
----o I Normal
AOC G I
Normal --osso----- 512K block ctr-----]-.-.:-:"
tr---,.
Fig. 1
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