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TB62715FN
8 BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT DRIVERS
TOSHIBA
TENTATIVE
TB62715FN
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TI62715FN
8 BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT DRIVERS
The TB62715FN is specifically designed for LED and LED
DISPLAY constant current drivers.
This constant current output circuits is able to set up
external resistor (IOUT = 70-150 mA).
This IC is monolithic integrated circuit designed to be used
together with Bi-CMOS process.
The devices consist of 8 bit shift register, latch, AND-GATE
& Constant Current Drivers.
FEATURES
SSOP20-P-225-0.65A
Weight : 0.14g (Typ.)
o Constant Current Output : Can set up all output current
with one resistor for 80 to 150 mA.
0 Constant Output Current Matching :
CURRENT CURRENT
HIGH / LOW "ll1rfllfssllD MATCHING MATCHING OUprlACg‘RENT
(BIT) (LOT) .
"L" a 0.7 v i 6.0% i 15.0% 2--70 mA
"H" 2 1.0V 16.0% 115.0% 50--150 mA
It Maximum Clock Frequency : fCLK=15 MHz
(Cascade Connected Operate, Top, = 25°C)
0 5V C-MOS Compatible Input
0 Package :
SSOP20-P-225-0.65A
980910EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to the foreign exchange and foreign trade laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
or other rights of the third
1999-03-16 1/11
TOSHIBA
TB62715FN
PIN CONNECTION (TOP VIEW)
LOGIC-GND t P 20 EIVDD
SERIAL-IN t 2 19 JR-EXT
CLOCK t 3 18 [ISERIAL-OUTi
/LATCH t 4 17 TSERIAL-OU"
HlGH/LOW t 5 16 J/EN/UUE
TB62715FN
POWER-GND t 6 15 raowER-tsND
OUTO t 7 14 Jour;
OUT1 t 8 13 Tours
OUT2 t 9 12 Tours
OUT? t 10 11 [loum
BLOCK DIAGRAM
OUTO OUT1 OUT7
R-EXT o-
l-REG.
HIGH/LOW T,
/ENABLE oif-,
/LATCH C - iy, l l ------
D Q 0 SERIAL-OUT?
SERIAL-IN C lip D Q D Q ------ D Q OSERIAL-OUT1
f" CK C' CK -y CK
CLOCK 0 li> . , -
TRUTH TABLE
CLOCK /LATCH /ENABLE SERIAL-IN OUTO ... OUTS ... OUT7 SERIAL-OUT
UP H L Dn Dn ... Dn - 5 ... Dn - 7 Dn - 7
UP L L Dn + 1 No Change Dn - 6
UP H L Dn+2 Dn+2-Dn-3-Dn-5 Dn-5
DOWN X L Dn+3 Dn+2-Dn-3-Dn-5 Dn-S
DOWN X H Dn + 3 Off Dn - 5
(Note) OUTO--OUT7 = on in case of Dn
H leveland OUTO--7 = off in case of Dn = level.
A resistor is connected with R-EXT and GND accompanied with outside, and it is
necessary that a correct power supply voltage is supplied.
1999-03-16 2/11
TOSHIBA
TB62715FN
TIMING DIAGRAM
CLOCK TI TI n n n n n TI 3x
i 5 i 5 i i i 5 5 5V
SERIAL-IN I 5 I I 5 I I E I I 5 I 3 0V
i i i i i 5V
ILATCH . . . . TI ov
/ENABLE
.Ll ov
OUTO I 2 8ff
OUT1 l-l n
. . Off
OUT3 , , Off
. . . On
OUT? . . . . . . . . I I Off
SERIAL-OUT] V / / / / / / / A . . (W
SERIAL-OUT? V / / x / / / / / Al il
(Note) Latches are level sensitive, not rising edge sensitive and not syncronus CLOCK.
Input of LATCH-terminal to H Level, data passes latches, and input to L level, data
hold latches.
Input of ENABLE-terminal to H level, all output (OUTO~7) do off.
TERMINAL DISCRIPTION
PIN No. PIN NAME FUNCTION
5 HIGH/LOW It is the terminal which does switching for the big current/low current.
6, 15 POWER-GND GND terminal for current output.
1 LOGIC-GND GND terminal for control logic.
2 SERIAL-IN Input terminal of a serial-data for shift-register.
3 CLOCK Input terminal of a clock for data shift to up-edge.
4 /LATCH Input terminal of a data strobe. Latches passes data with "H" level input of
LATCH-terminal, and hold data with "L'' level input.
3:331; OUTO~7 Output terminals.
Input terminal of output enable. All outputs (OUTO~7) do off with "H" level
16 /ENABLE . . . " " .
input of ENABLE-terminal, and do on with L level input.
18 SERIAL-OUT1 9 U -PJu5-'-9tD+fottili'cFCss4-o
17 SERIAL-OUT2 Output terminal of a serial-data for next SERIAL-IN terminal.
19 R-EXT Input terminal of connects with a resister for to set up all output current.
20 VDD 5V Supply voltage terminal.
1999-03-1 6 3/11
TOSHIBA TB62715FN
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
l. /ENABLE terminal 2. /LATCH terminal
VDD o-a
/LATCH CY-a
GND oi:""
/ENABLE C?,
GND LL"
3. CLOCK, SERIAL-IN terminal 4. SERIAL-OUT terminal
VDD o VDD
CLOCK, 0 8th F/F -1] SERIAL-OUT
SERIAL-IN DATA
GND 0 GND
1999-03-16 4/11
TOSHIBA TB62715FN
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD o-- + 7.0 V
Input Voltage VIN -0.4--VDD + 0.4 V
Output Current IOUT +150 (HIGH/LOW = "H") mA/ch
+70 (HIGH/LOW = "L")
Output Voltage VOUT -0.5-- + 17.0 V
Clock Frequency fCLK 15 MHz
GND Terminal Current IGND 1200 mA
Power Dissipation PDI FN-type : 0.71 (FREE AIR, Ta = 25°C) W
PD2 FN-type : 0.96 (ON PCB, Ta = 25°C)
. Rth (j-a)1 175 (FREE AIR) o
Thermal Resistance Rth(j-a)2 130 (ON PCB) C/W
Operating Temperature Topr -40-- +85 ''C
Storage Temperature Tstg - 55-- + 150 °C
(Note) FN type : Ambient temperature deleted above 25°C in the proportion of 7.69 mW/°C
Condition = On PCB (50 x 50 x 1.6mm Cu = 40%)
RECOMMENDED OPERATING CONDITION (Ta = 25°C unless otherwise noted)
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VOUT - - 15.0 V
DC 1 circuit
. . mA/ch
DC 1 circuit
Output Current IOUT2 (HIGH/LOW = "L") 2 - 60
IOH SERIAL-OUT1, 2 - - - 1.0 mA
IOL SERIAL-OUT1, 2 - - 1.0
VIH 0.7VDD - VDD + 0.3
I V I V
nput o tage VIL - 0.3 - th31/DD
LATCH Pulse Width tw LAT 100 - - ns
CLOCK Pulse Width tw CLK 50 - - ns
Set-up Time for DATA tsetup(D) 60 - - ns
Hold Time for DATA thold (D) 20 - - ns
Set-up Time for LATCH tsetup(L) 100 - - ns
Hold Time for ENABLE thold (L) 60 - - ns
V = 4.5--5.5 V,
Clock Frequency fCLK CaDSIZade Operation 10.0 - - MHz
Power Dissipation PD Ta = 85°C (FN-type On PCB) - - 0.50 W
1999-03-1 6 5/11
TOSHIBA TB62715FN
ELECTRICAL CHARACTERISTICS (Ta = 25°C unless otherwise noted)
CHARACTERISTIC SYMBOL (li] CONDITION MIN. TYP. MAX. UNIT
Input "H" Level VIH - 0.7VDD - VDD V
Voltage "L" Level VIL - GND - 0.31/DD
tetLeakage IOH VOH = 15.0v - - 10 pA
Output SERIAL VOH IOH = -1.0 mA - - 0.4 V
Voltage -OUT1, 2 VOL IOL = +1.0 mA 4.6 - -
Output Current 1 IOL1 VCE = 0.7V REXT = 520 n, 31.7 37.5 43.1 mA
|Current Skew dIOL1 HIGH/LOW = "L" - 11.5 16.0 %
Output Current 2 IOL2 VCE = 1.0V REXT = 160 fl, 104.0 123.0 141.4 mA
(Current Skew dlOL2 HIGH/LOW = "H" - 31.5 i6.0 %
Supply 1./oltage % /VDD Ta = -40- +85°C - + 1.5 +5.0 % /1/
Regulation
Pull-up Resistor RIN(up) 100 200 400 kit
Pull-down Resistor RIN (down) 100 200 400
IDD (off)1 REXT = OPEN OUTO--7 = off - 1.0 2.0
Supply "OFF" IDD (off) 2 REXT = 260 n OUTO~7 = off - 10.0 15.0
Current IDD (off) 3 REXT = 160 n OUTO--7 = off - 16.0 21.0 mA
"ON" IDD (on)1 REXT = 260 n OUTO--7 = on - 23.1 40.5
IDD (on) 2 REXT = 160 n OUTO--7 = on - 33.0 62.1
SWITCHING CHARACTERISTICS (Ta = 25°C unless otherwise noted)
CHARACTERISTIC SYMBOL 153T CONDITION MIN. TYP. MAX. UNIT
. SlN-OUTn - 500 1000
'l',r2l,'rirt,i,1n LATCH-OUTn 2 - 500 1000
"e y 'Te" ENABLE-OUTn tpLH - 500 1000 ns
( L To H )
CLK-SOUTn - 30 70
. SlN-OUTn VDD = 5.0V - 500 1000
'J2'lri,t,it,n LATCH-OUTn 2 VCE = 1.0V - 500 1000
f y "Ce" ENABLE-OUTn tPHL VIH = VDD, - 500 1000 ns
( H To L ) CLK-SOUTn VIL = GND - 30 70
REXT = 260 n,
Pulse Width CLK tw CLK, /CLK 2 RL = 32 n - 20 30 ns
LATCH tw LAT, /LAT IOUT = 125 mA, - 10 25
Set-Up Time for L-H tsetupLAT 2 CL = 10.5 pF - 25 50 ns
LATCH/SIN H-L &SIN tor : 10% to 90% - 25 50
Hold Time for L-H thold 2 tof : 90% to 10% - 0 15 ns
LATCH/SIN H-L LAT/SIN tpLH: 50% to 10% - 0 15
Maximum CLOCK Rise Time tr 2 tpHLI 50% to 90% - - 10 ps
Maximum CLOCK Fall Time tf 2 - - 10 #5
Output Rise Time tor 2 300 600 1000 ns
Output Fall Time tof 2 300 600 1000 ns
1999-03-1 6 6/11
TOSHIBA
TB62715FN
TEST CIRCUIT
DC characteristic
AC characteristic
VIH, VIL
fr SW-MATRIX
SERIAL-OUT1, 2
o-C ENA-BLE
o-C) CLOCK
o-C LAT-CH
o-C. SERIAL-IN
R-EXT L-GND P-GND
SERIAL-OUT1, 2
-(2 ENA-BLE
-C CLOCK
-C) LAT-CH
-C SERIAL-IN
R-EXT L-GND P-GND
1999-03-16 7/11
TOSHIBA
TB62715FN
TIMING WAVEFORM
1. CLOCK-SERIAL OUT, OUTn
SERIAL Pl £50%
SERIAL OUT,
OUTn (current)
2. CLOCK-ILATCH
SERIAL IN
/ LATCH
3. /ENABLE-OUTn
IENABLE
(Current Wave Form)
tsetu p
j/soy,
- "L" level = DATA HOLD
tsetu p
1999-03-1 6 8/11
TOSHIBA
(mA/bit)
(W/IC)
POWER DISSIPATION PD
IOUT - DUTY CYCLE
Ta = 25 (°C)
Ta = 60 CC)
40 VDD = 5.0V
Tj = 120°C
20 8 bit Active
VCE = 1.0V
0 20 40 60 80 100
DUTY CYCLE (%)
co ON PCB
© FREE AIR
-40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE Ta (°C)
LED DRIVER T86270X SERIES APPLICATION NOTE
(mA/ brt)
R-EXT - IOUT
HIGH/LOW = "H"
HIGH ILOW = "L"
1 00 1 000 1 0000
R-EXT (Q)
(mA/bit)
(mA / but)
TB62715FN
IOUT - DUTY CYCLE
Ta = 25 (°C)
Ta = 60 CC)
Ta = 85 (°C)
VDD = 5.0 V
Tj = 120°C
8 bit Active
VCE = 0.7V
20 40 60 80 100
DUTY CYCLE (%)
R-EXT - IOUT
HIGH /LOW = "H"
HIGH /LOW = "L"
1000 10000
R-EXT (Q)
1999-03-1 6 9/11
TOSHIBA TB62715FN
TOTAL SUPPLY VOLTAGE (VLED)
This device can operate 0.7--1.0V (V0).
When a higher voltage is input to the device, the excess voltage is consumed inside the device, that
leads to power dissipation.
In order to minimize power dissipation and loss, we would like to recommend to set the total
supply voltage as shown below,
VLED (total supply voltage) = VCE (Tr Vsat) + Vf (LED Forward voltage) + vo (IC supply voltage)
When the totalsupply is too high considering the power dissipation of this device, an additional R
can decrease the supply voltage.
VLED - Vf(LED) - Vo(Min.)
R = IO (Max.) x BIT(Max.)
PATTERN LAYOUT
This device owns only one ground pin that means signal ground pin power ground pin are common. If
ground pattern layout contains large inductance and impedance, and the voltage between ground and
LATCH, CLOCK terminals exceeds 2.5V by switching noise in operation, this device may miss-operated.
So we would like you to pay attention to pattern layout to minimize inductance.
APPLICATION CIRCUIT
VLED = 3~4(v)
C ENABLE OUTO
w CLOCK l L R
J‘ - , I
v LATCH l
C SERIAL-IN OUT7 CD-
R-EXT GND SERIAL-OUT1, 2
C ENABLE OUTO
C CLOCK E
C LATCH l
_ SERIAL-IN OUT7
R-EXT L-GND $ERIAL-OUT1, 2
1999-03-1 6 10/11
TOSHIBA
OUTLINE DRAWING
SSOP20-P-225-0.65A
HHHHHHHHEH
4.41202 :
7.0MAX
Weight : 0.14g (Typ.)
C) I 1
EH lie t H
0.325TYP -.iv1llst-t-11ar,,is,:i,s
0:15 .095
TB62715FN
Unit : mm
(225mil)
l 1 0.45:t0.2
www.ic-phoenix.com
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