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TB62707F
8BIT LATCHES & CONSTANT CURRENT DRIVERS
TOSHIBA
TB62707F
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62707F
SBIT LATCHES & CONSTANT CURRENT DRIVERS
The TB62707F is specifically designed for LED and LED
DISPLAY constant current drivers.
This constant current output is able to set up external
resistor (IOUT = 90mA MAX.).
This IC is monolithic integrated circuit designed to be
used together with Bi-CMOS process.
The devices consist of 8bit latches, AND-GATE and
Constant Current Drivers.
FEATURES
0 Constant Current Output :
Can set up all output current with one resistor for 5 to 90mA.
o Constant Output Current Matching :
SSOP24-P-300-1.00
Weight : 0.32g (Typ.)
OUTPUT-GND CURRENT OUTPUT
VOLTAGE MATCHING CURRENT
20.4 [V] $6.0 [%] 5--40mA
20.7 [V] $6.0 [%] 40--90mA
0 5V CMOS Compatible Input
0 Package : SSOP24-P-300
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
or other rights of the third
1998-06-11 1/11
TOSHIBA TB62707F
PIN CONNECTION (Top view)
LAT-CH E l VDD
EN_tBLE E C) Cl REXT
NC E l P-GND
INO E . OUTO
|N1 E Cl OUT1
IN2 E l OUT2
IN3 E l OUT3
IN4 E l OUT4
IN5 E l OUTS
INS E l OUTG
IN7 E l OUT7
L-GND E l P-GND
BLOCK DIAGRAM
VDD CY- ........ OUTO OUT1 OUTZ OUT3 OUT4 OUTS OUTG OUT7
REXT w d>d>d>d>d>d>d> OP-GND
VVVVVVV
CURRENT MIRROR CIRCUIT
i)))))))) ot:0-osNA-LE
LATCH o- BBIT LATCHES
llllllll-OL-GND
INO INI IN2 IN3 IN4 INS IN6 IN7
TIMING DIAGRAM
PIO--? I-I i-l Firm. 3:
ENABLE
OUTO--7
_.__l LI-U,, l l l l l LrLrLC,''n1
(Note) Latches are level sensitive, not rising edge sensitive and not synchronous CLOCK.
Input of 'L7i"rtlTT-terminal to "H" level, data passes latches, and input to "L'' level, data
hold latches.
Input of ENABLE-terminal to "H" level, all output (OUTO~7) do off.
1998-06-11 2/11
TOSHIBA
TERMINAL DESCRIPTION
TB62707F
PIN No. PIN NAME FUNCTION
1 Ttteq Input terminal of a data strobe. Latches passes data with "H" level input of
LATCH-terminal, and hold data with "L" level input.
- Input terminal of output enable. All outputs (OUTO~7) do off with "H" level
2 ENABLE . - . . " " .
input of ENABLE-terminal, and do on with L level input.
4~11 INO--7 Input terminal of a parallel-data for latches.
3 NC No connection.
12 L-GND GND terminal for controll logic.
13 P-GND GND terminal for output constant current drivers.
14--21 OUTO--7 Output terminals.
22 P-GND GND terminal for output constant current drivers.
23 REXT Input terminal of connects with a resister for to set up all output current.
24 VDD 5V Supply voltage terminal
TRUTH TABLE
INO--7
LATC H
ENABLE OUTO~7
III—II—Ir—
II—I—I—I—I—i—
1998-06-11 3/11
TOSHIBA
EQUIVALENT CIRCUIT OF INPUTS
1. ENABLE terminal
3. CLOCK, SERIAL-IN terminal
CLOCK,
SERIAL-IN
TB62707F
2. LATCH terminal
LATCH o
'r'""",
4. SERIAL-OUT terminal
VDD 0—
8th LATCH SERIAL OUT
DATUM -
GND 0 GNDCy-
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VCC 7.0 V
Input Voltage VIN -0.3--VDD +0.3 V
Output Current Io 90.0 mA
Output Voltage vo -0.3--17.0 V
GND Terminal Current IGND 720 mA
Power Dissipation PD 780 (*) mW
Operating Temperature Top, -40--85 "C
Storage Temperature Tstg - 55~150 "C
(*) On PCB(50x50x1.6mm Cu 30% Glass Epoxy PCB)
Ambient temperature deleted above 25°C in the proportion of 6.66mW/°C
1998-06-11 4/11
TOSHIBA TB62707F
RECOMMENDED OPERATING CONDITION (Ta-- -40--85oC unless otherwise noted)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Supply Voltage VDD - 4.5 5.0 5.5 V
Output Voltage vo - - - 15.0 V
IOUT DC1 circuit 5.0 - 88 mA
Output Current IOH SERIAL-OUT - - - 1.0 mA
IOL SERIAL-OUT - - 1.0 mA
VIH - 0.7 VDD - VDD + 0.3
Input Voltage VIL - -0.3 - 0.3 VDD V
_....-...-....-....-.....- . tw LAT 100 - -
LATCH Pulse Width tw Ltrr 100 - - ns
INPUT Pulse Width 'tr, [l', eg - - ns
VDD =4.5V--5.5V
- . tw EN 4500 - -
ENABLE Pulse Width tw TNI" 4500 - - ns
Set-Up Time for LATCH tsetup (L) 100 - - ns
Hold Time for ENABLE thold (L) 100 - - ns
Power Dissipation PD ON PCB, Ta=85°C - - 0.60 W
ELECTRICAL CHARACTERISTICS (VDD= 5.0V, Ta =25°C unless otherwise noted)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Input "H" Level VIH - - 0.7 VDD - VDD V
Voltage "L" Level VIL - - GND - 0.3 VDD
Output Leakage -
Current IOH - l/OH =15.0V - 10 PA
Output - VOL - IOL =1.0mA - - 0.4 v
Voltage SERIAL OUT VOH - IOL= -1.0mA 4.6 - - V
|OL1 - VCE=0.7V REXT=6200 35.7 42.0 48.3 mA
Output Current 1 IOLZ - VCE =o.4v (Include skew) 68.0 80.0 92.0 mA
Current Skew AIOL'I - I62: Cltlt REXT = 6200 - i 1.5 i 6.0 %
IOL3 - VCE = 0.7V REXT = 3300 64.2 75.5 86.8 mA
Output Current 2 IOL4 - VCE =0.7V (Include skew) 63.8 75.0 86.2 mA
Current Skew AIOL2 - (ei, 33%; REXT = 3300 - i 1.5 i 6.0 %
Supply Voltage 0 - - - - -- 0 - - 0
Regulation 4) NW REXT -4700, Ta - 40 85 c + 5.0 A: /V
Reference Voltage Vref - - - 1.26 - V
REXT=OPEN, OUTI--8 =off,
IDD (OHM - VDD=4.5V, ENABLE = "H" - 0.6 1.2
" n R = 5000, OUT1--8 = off,
Supply Current OFF IDD (off) 2 - V33: 4.5V, tTq7gTg= "H" 6.0 8.0 10.0 mA
REXT = 280.0, OUT1--8 = off,
R = Q T1~8 =
IDD(on)1 - EXT_ 500 1f,iy,rf,,) ?n' 8.0 13.0 20.0
n " 1/DD=4.5V, ENABLE - L
Supply Current ON mA
I REXT=2800~ OUT1--8=on, 18 0 25 0 35 0
DD (on) 2 - VDD =4.5v, ENABLE = "L" . . .
1998-06-11 5/11
TOSHIBA TB62707F
SWITCHING CHARACTERISTICS (Ta=25°C, unless otherwise noted)
TEST TEST
CHARACTERISTIC SYMBOL CIR- MIN. TYP. MAX. UNIT
CUIT CONDITION
Propagation Delay |N-OUTn - - 600 1200
Time CL'' to "H") m-OUTn tpLH - - 600 1200 ns
m-OUTn - - 600 1200
Propagation Delay lN-OUTn - - 300 1200
Time CH'' to "L") m-OUTn tpHL - VDD=5-0V - 300 1200 ns
ENABLE-OUTn - VCE = 0.4V - 300 1200
Pulse Width IN tw IN, IN - VIH =VDD - 2000 3500
LATCH tw LAT, LAT - lhL=0V - 25 50 ns
m tw ENA, m - REXT=5000 - 2000 3500
Set-Up Time for L-H - - IOUT=40mA - 25 50
LATCH & CLOCK H-L tsetup LAT - VL=3-0V - 25 50 ns
HoldTimefor L-H - - RL=650 - 0 15
LATCH & CLOCK H-L thold LAT - CL=10-SPF - 0 15 ns
Maximum CLOCK Rise Time tr - - - 10 ,us
Maximum CLOCK Fall Time tf - - - 10 ,as
Output Rise Time tor - 200 1000 1200 ns
Output Fall Time tof - 200 1000 1200 ns
TOSHIBA
TB62707F
DC CHARACTERISTICS TEST CIRCUIT
o-C ENABLE VDD OUTO D-o
'le Ill. o-C) CLOCK E IOL
- o-C LAT-CH oulT7 D-o
VIH, VIL REXT GND
'ref E) 3?
AC CHARACTERISTICS TEST CIRCUIT
','/ife. VIL -CENA-BLE VDD oum ( Y-etc-
-CD CLOCK E CL
SW-MATRIX C.] LATCH OUIT7 RL -
-C an 'iF-"
REXT GND
PRECAUTIONS for USING
Utmost care is necessary in the design of the output line, VCC (VDD) and GND (L-GND, P-GND) line
since IC may be destroyed due to short-circuit between outputs, air contamination fault, or fault
by improper grounding.
1998-06-11 7/11
TOSHIBA TB62707F
TIMING WAVEFORM
l. INn-OUTn
an 50%Z thK l 50% -sa:s,z"l,
tpLH tpHL
2. ENABLE-OUTn
ENABLE 50%\\ //50%
tpLH a o
OUTn 50 /o 50 A)
3. LATCH-OUTn
LATCH 50%; 50% ay,, N
tpLH o o
OUTn 50 A: 50 A)
1998-06-11 8/11
TOSHIBA
IQUT - DUTY CYCLE
vo=o.4(v)
A v =0.7 v
I o ( )
VDD=5V
20 Tj=120°C(MAX.)
8BIT ACTIVE
Ta=25°C
0 20 40 60 80 100
DUTY CYCLE (%)
IQUT - DUTY CYCLE
80 Vo=0.4(V)
"ms 60
3 40 vo=0.7(v)
Tj=120°C (MAX.)
BBIT ACTIVE
Ta = 85°C
0 20 40 60 80 100
DUTY CYCLE (%)
LED DRIVER T86270X SERIES APPLICATION NOTE
(mA/blt)
Fig.1 REXT - IOUT
120 IOUT={1.26/REXT(Q)}><20
100 200 300 500 1000
2000 3000 5000
REXT (Q)
(mA/CH)
TB62707F
IQUT - DUTY CYCLE
vo = on (V)
vo = 0.7 (V)
VDD = 5V
Tj = 120°C (MAX.)
SBIT ACTIVE
Ta = 60°C
20 40 60 80 100
DUTY CYCLE (%)
1998-06-11 9/11
TOSHIBA TB62707F
[1] Output current (IOUT)
IOUT is set by the enternal resistor (R-EXT) as shown in Fig.1.
[2]Tota| supply voltage (VLED)
This device can operate 0.4--0.7V (V0).
When a higher voltage is input to the devide, the excess voltage is consumed inside the device, that
leads to power dissipation.
In order to minimize power dissipation and loss, we would like to recommended to set the total
supply voltage as shown below.
VLED (Total supply voltage)
=VCE (Tr Vsat) +Vf (LED Forward voltage) +Vo (IC supply voltage)
When the total supply is too high considering the power dissipation of this devide, an additional R
can decrease the supply voltage (V0).
APPLICATION
VLED = 3--4 (v)
f 1L ' l:
c, ENABLE ou,TO D
{] LATCH l
REXT L-GND P-GND
-C, ENABLE OUITO
w LATCH l
-c INn OUT7
REXT L-GND P-GND
[3] Pattern layout
This device owns only one ground pin that means signal ground pin and power ground pin are
common.
If ground pattern layout contains large inductance and impedance and the voltage between ground
and LATCH, CLOCK terminals exceeds 2.5V by switching noise in operation, this device may miss-
operate. So we would life you to pay attention to pattern layout to minimize inductance.
1998-06-11 10/11
TOSHIBA
OUTLINE DRAWING
SSOP24-P-300-1.00
24 tl ----
"lqlriplqririlqrlpllq J h"
6.0i0.2
13.5MAX
13.0i0.2
th4hthl r1
jaw ldl::litl:ysct---'-r.
1.utlT-Ye. ii :4tTt)Vtjiiyi
Weight : 0.329 (Typ.)
TB62707F
Unit : mm
7.9:03
(300mil)
0 5252120 dt
1998-06-11 11/11
www.ic-phoenix.com
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