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TB62200AF
DUAL-STEPPING MOTOR DRIVER IC USING PWM CHOPPER TYPE
TOSHIBA TB62200AF
TOSHIBA Bi-CMOS PROCESSOR IC SILICON MONOLITHIC
TB62200AF
DUAL-STEPPING MOTOR DRIVER IC USING PWM CHOPPER TYPE
FEATURES HSOP36-P-450-0.65
The TB62200AF is a dual-stepping motor driver driven by
chopper micro-step pseudo sine wave.
To drive two-phase stepping motors, Two pairs of 16-bit
latch and shift registers are built in the IC. The IC is
optimal for driving stepping motors at high efficiency and
with low-torque ripple.
The IC supports Mixed Decay mode for switching the
attenuation ratio at chopping. The switching time for the
attenuation ratio can be switched in two stages according
to the load.
W . ht 2 0.79 T .
Chopping bipolar stepping motor driver erg g ( yp.)
Two stepping motors driven by micro-step pseudo sine wave are controlled by a single driver IC
Monolithic Bi-CMOS IC
Low ON-resistance of RDS (on) = 0.5 Q (@Tj = 25°C, 1.0A : Typ.)
Two pairs of built-in 16-bit shift and latch registers
Two pairs of built-in 4-bit D/A converters for micro steps
Built-in TSD, VDD & VM power monitor (reset) circuit for protection
Built-in charge pump circuit (two external capacitors)
36-pin power flat package (HSOP36-P-450-0.65)
Output voltage : 30V max
Output current : 1.3 A/phase max
Built-in Mixed Decay mode (Fast/Slow at 40/74% switchable) and Slow Decay mode
Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at
100 kHz or higher.
(Note I) When using the IC, pay attention to thermal conditions.
(Note 2) These devices are easy damage by high static voltage.
In regards to this, please handle with care.
980910EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to the foreign exchange and foreign trade laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert or other rights of the third
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1999-03-09 1/56
TOSHIBA TB62200AF
BLOCK DIAGRAM 1
Overview (Power lines : A/B unit (C/D unit is the same as A/B unit))
Block Diagram (Power lines)
Output
control
Output
circuit
circuit
Full Bridge
Rosc AB
Analog
circuit,
Current
com pare
circuit, OSC
oscillator
circuit
Cosc AB
Output
circuit
Vref 9
Full Bridge
Logic circuit
CLK Charge
STROBE l
circuit
4/15/22/33
Vss (FIN) i' IPGND
- High-voltage wiring (VM & VH)
Low-voltage wiring (VDD)
........ GND wiring (PGND)
_............. GND wiring (USS)
- Control signal wiring (LOGIC)
1999-03-09 2/56
TOSHIBA
BLOCK DIAGRAM 2
Overview (Details)
CLK AB
16-bit shift
DATA AB
register
CLK CD 2
16-bit shift
DATA CD 2 _
register
STROBE AB
Current A
Decay A
PHASE A
MIXED DECAY
MODE A
16-bit latch
register
Current B
Decay B
PHASE B
TORQUE AB
MIXED DECAY
MODE B
Current C
Decay C
PHASE C
MIXED DECAY
MODE C
16-bit latch
register
Current D
Decay D
PHASE D
TORQUE CD
MIXED DECAY
MODE D
STROBE CD
TB62200AF
Vref AB A B
Output
control circuit
Output
control circuit
Output
control circuit
Output
control circuit
Vref CD
1999-03-09 3/56
TOSHIBA TB62200AF
BLOCK DIAGRAM 3
Output control circuit A/B unit (C/D unit is the same as A/B unit)
VDD DECAY A PHASE A DECAY A A B C
Rosc AB
MIXED OUT VMA
c DECAY CONTROL A
OSC AB TIMMING Full Bridge
l Converter
Bipolar
Current A (C) 1 Output
TORQUE 1 TORQUE ANGLE
CONTROL
TORQUE 2 CONTROL (D/A)
Full Bridge
VrefAB Converter
OUT Bipolar
MIXED DECAY B 2 CONTROL Output
4/5/6/7 8 3
Current B PHASE B DECAY B
(*) Symbols
l/SS (signal ground) pin (FIN)
(ii) External I/O pin
Ci) Serial input data. Circled numbers correspond to serial data numbers at input.
A chopping reference oscillation waveform (saw-tooo wave) is generated by the resistor and
capacitor connected to the CR pin. Current path switching timing is generated for Mixed and Slow
Decay modes according to the chopping waveform.
The reference voltage applied to the Vref pin is attenuated by 100, 85, 70, or 50% according to the
2-bit torque data. A reference voltage is generated by the attenuated reference voltage and 4-bit
current setting data.
When current flows through the sense resistor connected to the Rs pin, there is a potential
difference between the VM and Rs pins. The potential difference is compared by the comparator
and the result fed back to the output control circuit. Then chopping takes place.
1999-03-09 4/56
TOSHIBA TB62200AF
BLOCK DIAGRAM 4
Input A/B unit (C/D unit is the same as A/B unit)
1. Logic input circuit (CLK, DATA, STROBE)
- To Logic IC
25, 26, 29, 30, 31
- To D/A circuit
3. CR circuit block
VDD 27 '
CR I l
2. Vref input circuit
VDD 27
10m and) 3kQ 3kQ 80k!)
C Crt:::--
4:; Comp
o 512 -
o M . .
m Comp - To Mixed Decay signal
915 - COPM equivalent circuit
Comp VDD -
+ Comp+ IN si- Comp- IN
(pls. - - o-,
Comp Out
GND FIN . GND
1999-03-09 5/56
TOSHIBA TB62200AF
BLOCK DIAGRAM 5
Output A/B unit (C/D unit is the same as A/B unit)
l'' To VM supply
-,,_(30-,,N-
Rs A Ms A
Full Bridge ' '
converter , ,
From U1 1 1 U2
output bipolar ='atEE T T a
control i i Output A
circuit output t .," 62h,
control i i Output l:
circuit L1
Phase A
r1\ VM B
Rss‘ RRSB
Full Bridge
From converter C: '
output bi I U E E U
I 0 ar . .
cpntfol p 1 E T I 2
curcuut output : :' Output B fp, -rTTP-
control 3 g - I
circuit 5 1 Output B I , (ii)
L 5 .' L 'dy
_1.E T. I 2
Phase B 5 E
1999-03-09 6/56
TOSHIBA
TB62200AF
PIN ASSIGNMENT
(TOP VIEW)
VMBE 1 36 JVMA
OUTB[2 3SJOUTK
RSBE 3 34 JRSA
PGNDE 4 33 JPGND
ourirs 32]OUTA
rocr 6 31 JSTROBE AB
CcpA[ 7 30 JCLK AB
CR AB r 8 29 l DATA AB
Vref ABE 9 281%
Vss(FIN) T B 6 2 2 0 0 A F Vss(FIN)
Vref cot 10 27 IV»
CR cot 11 26 JDATA CD
Cch[ 12 25 JCLK CD
Ccp " 13 24 JSTROBE CD
OUT_D[14 23]ourc
PGND[ 15 22 JPGND
RSDE 16 21 JRsc
OUTDE 17 20]OUTE
wwor 18 19 JVMC
Rs A~D : Current sense resistor connecting pins
PGND : Power GND
NC : Not connected
1999-03-09 7/56
TOSHIBA
TB62200AF
PIN DESCRIPTION
['lll PIN SYMBOL DESCRIPTION
1 VM B Power pin for output B block
2 OUT B Output B pin
3 Rs B Channel B current pin
4 PGND Power GND pin (Note)
5 OUT B Output g pin
6 NC Not connected
7 Ccp A Capacitor pin for charge pump (Ccp1)
8 CR AB External C/R (osc) pin AB (sets chopping frequency)
9 Vref AB Vref input pin AB
FIN VSS FIN Nss) : Logic GND pin (Note)
10 Vref CD Vref input pin CD
11 CR CD External C/R (osc) pin CD (sets chopping frequency)
12 Ccp B Capacitor pin for charge pump (Ccp2)
13 Ccp C Capacitor pin for charge pump (Ccp2)
14 OUT 5 Output 6 pin
15 PGND Power GND pin (Note)
16 Rs D Channel D current pin
17 OUT D Output D pin
18 VM D Power pin for output D block
19 VM C Power pin for output C block
20 OUT E Output E pin
21 RSC Channel C current pin
22 PGND Power GND pin (Note)
23 OUT C Output C pin
24 STROBE CD CD STROBE (latch) signal input pin cf-.. LATCH)
25 CLK CD CD clock input pin
26 DATA CD CD serial data signal input pin
27 VDD Power pin for logic block
FIN vss FIN NSS) : Logic GND pin (Note)
28 FSET Output reset signal input pin (L : RESET)
29 DATA AB AB serial data signal input pin
30 CLK AB AB clock input pin
31 STROBE AB AB STROBE (latch) signal input pin CC: LATCH)
32 OUT A Output A pin
33 PGND Power GND pin (Note)
34 RSA Channel A current pin
35 OUT 'h"" Output 7i- pin
36 VM A Power pin for output A block
(Note) How to handle GND pins
All power GND pins and FIN (V55 : signal GND) pins must be grounded.
Since FIN also functions as a heat sink, take the heat dissipation into consideration
when designing the board.
1999-03-09 8/56
TOSHIBA TB62200AF
SIGNAL FUNCTIONS
1. Serial input signals (for A/B. C/D is the same as A/B)
DATA No. NAME FUNCTIONS
0 TORQUE 0 DATA No.0, 1= HH : 100%, LH : 85%
1 TORQUE 1 HL : 70%, LL : 50%
2 MIXED DECAY MODE B (H : 74% FAST DECAY, L : 40% FAST DECAY)
3 DECAY B (H : SLOW DECAY, L : MIXED DECAY)
4 Current Bo Used for setting current.
5 Current B1 (LLLL = Output ALL OFF MODE)
6 Current B2 4-bit current B data
7 Current B3 (Steps can be divided into 16 by 4-bit data) (Note 1)
8 PHASE B Phase information (H : OUT B : H, OUT B : L)
9 MIXED DECAY MODE A (H : 74% FAST DECAY, L : 40% FAST DECAY)
10 DECAY A (H : SLOW DECAY, L : MIXED DECAY)
11 Current A0 Used for setting current.
12 Current A1 (LLLL = Output ALL OFF MODE)
13 Current A2 4-bit current A data
14 Current A3 (Steps can be divided into 16 by 4-bit data)
15 PHASE A Phase information (H : OUT A : H, OUT A : L)
(Note 1) Serial data input order
Serial data are input in
2. Serial input signal functions
the order DATA 0(TORQUE 0)-eDATA 15(PHASE A).
INPUT Action
- VDDR
CLK (JSTCZZE) DATA RESET 9&1”? OPEEAPFION
_f" x x H H L No change in shift register.
1 x H H H L H level is input to shift register.
1 x L H H L L level is input to shift register.
x _f" x H H L Shift register data are latched.
x l x H H L Qn
x x x L x L Output off (shift register data clear)
x x x x L L Output off (shift register data clear)
x x x H H H Output off (sh.ift register data hold)
Charge pump In operation
x : Don't Care
Qn : Latched output level when STROBE is J.
H when TSD is in operation.
(Note 2) VDDR and VMR
H when the operable range (3V typical) or higher and L when lower.
3. PHASE functions
INPUT FUNCTION
H Positive polarity (A : H, A : L)
L Negative polarity (A : L, A : H)
1999-03-09 9/56
TOSHIBA TB62200AF
4. DECAY functions
INPUT FUNCTION
H Slow Decay Mode
L Mixed Decay Mode
5. Mixed Decay Mode functions
INPUT FUNCTION
H 74% Mixed Decay Mode
L 40% Mixed Decay Mode
(Note) Valid only when DECAY signal is L (Mixed Decay Mode).
6. TORQUE functions
TORQUE 0 TORQUE 1 Comparator reference voltage
H H 100%
L H 85%
H L 70%
L L 50%
7. Current Ax (Bx) functions
STEP ANGLE
16 90.0
15 84.4
14 78.8
13 73.1
12 67.5
11 61.2
10 56.3
l—I—l—l—I—I—l—l—IIIIIIIII
r—r—III—I—IIr—I—IIl—l—III
l—II—II—Il—II—Il—Ir—II—II
r—r-I-I—IIIII—I—I-r—IIIII
IIIIIIIIII—I—I—I—I—I—I—I—
IIIIII—I—l—I—IIIII—I—I—I-
IIIr—r—IIr—r—IIr—I—IIr—I—
III—II—II—II—II—II—II—Il—
By inputting the above current data (A '. 4-bit, B : 4-bit), 17-microstep drive is possible. For 1 step
fixed to 90 degrees, see the section on output current vector line (54 page).
1999-03-09 10/56
TOSHIBA
8. Serial Data Input Setting
DATA (0)(1)(2)(3Xo)(s)(6)(7)(is)(9)(i)(12)(iX1sl
CLK -nflflflflflflflflflflflflflflfLC"
STROBE ------------------------------------ rl:
(*) Data input to the DATA pin are 16-bit serial data.
Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A).
transferred at the following timings.
0 At CLK falling edge
It At CLK rising edge
: data input
: data transfer
TB62200AF
Data are input and
After data are transferred, all data are latched on the rising edge of the STROBE signal.
As long as STROBE is not rising, the signal can be either Low or High during data
transfer.
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Logic Supply Voltage VDD 7 V
Output Voltage VM 30 V
Output Current Iout 1.3 (Note 1) A/phase
Current Detect Pin Voltage VRS VM - 1.0 V
Charge Pump Pin Maximum
Voltage (CCP1 Pin) VH VM + 7.0 V
Logic Input Voltage VIN --VDD + 0.4 V
1.4 (Note 2) W
. . . P
Power Dissipation D 3.2 (Note 3) W
Operating Temperature Topr -40-85 °C
Storage Temperature Tstg - 50--150 "C
(Note 1) Perform thermal calculations for instantaneous current value and the maximum
current value under normal conditions. Use the IC at 1.0A or less per phase.
(Note 2) Measured for the IC only.
(Note 3) Measured when mounted on the board. (90 x 230 x 1.6mm) (Ta = 25°C)
RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 85°C)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Logic Supply Voltage VDD - 4.5 5.0 5.5 V
Output Voltage VM VDD = 5.0V 20 24 30 v
Output Current lout Ta = 25°C, per phase - 0.9 1.0 A
Logic Input Voltage VIN - GND - VDD V
Clock Frequency fCLK VDD = 5.0V 1.0 - 25 MHz
Chopping Frequency fchop VDD = 5.0V 32 100 150 MHz
VDD = 5.0 v, VM = 24 v, VDD
Reference Voltage Vref Torque = 100% 2.0 3.0 - 1.0 V
1999-03-09 11/56
TOSHIBA TB62200AF
ELECTRICAL CHARACTERISTICS 1 (unless otherwise specified, Ta = 25°C, VDD = 5V, VM = 24V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
HIGH VIN (H) 2.0 - lee,
Input Voltage 1 CLK, RESET, STROBE, DATA pins . V
LOW V GND 0.8
IN (L) - 0.4 - .
I -r_r_r...r_r_rV . - - 1.0
Input Current IN(H) 1 CLK, STROBE, RESET, DATA pms pA
IIN (L) - - 1.0
VDD = 5V (STROBE, RESET,
IDD1 DATA = L), RESET = L, - 4.0 6.0
Power Dissipation 1 Logic, output all off mA
(VDD pin) Output OPEN, fCLK = 6.25 MHz
IDD2 LOGIC ACTIVE, VDD = SV, - 4.0 20
Charge Pump = charged
Output OPEN (STROBE, CLK,
DATA = L), RESET = L,
IMI Logic, output all off - 4.5 8
Charge Pump = no operation
3 Output OPEN, fCLK = 6.25 MHz
Power Dissipation LOGIC ACTIVE, VDD = 5V,
(VM pin) Wl2 VM = 24V, Output off - 12 20 mA
Charge Pump = charged
Output OPEN, fCLK = 6.25 MHz
LOGIC ACTIVE, 100 kHz chopping
Wl3 4 (emulation), Output OPEN, - 30 40
Charge Pump = charged
tet Standby Upper IOH ),/P-iiE-; [lt -L2/1hltt , ov, -400 - - M
tet Bias Upper '03 2 :23; :meiflTXl Jtl l 24 V, - 200 - - A
[e,t,':t,Leaka9e Lower IOL -)(-iy-ii-t-ir:. I=/il = CcpA = Vout = 24 V, - - 1.0 i“
(Reggie) VRs(H) 1rafa3/yi/.tf=(tt,1)a=sjt/" - 100 -
$2355? Jil VRS (MH) 5 ")r/ioeRfo=ui/-rvi11(crf=fi;.irri) SL1 /5.1 83 85 87 %
Voltage Ratio Pg; VRS (ML) 1r,e/i"d0=1e)e,f=(t1rl)si",t1 / 5.1 68 70 72
LOW VRS (L) 1rafa3/yc.1de=f(1all)se=t1/'1 48 50 52
fliu2,uetntciTent mom 6 Iout = 900 mA - 5 - 5 %
ggggngglrrent Setting Aloutz 6 Iout = 900 mA - 10 - 10 %
. VRS = 24V, VM = 24V,
RS Pin Current IRS 7 "rt-trift-T"'"' = L (RESET status) - - 5 “A
1999-03-09 12/56
TOSHIBA TB62200AF
ELECTRICAL CHARACTERISTICS 1 (unless otherwise specified, Ta = 25°C, VDD = 5V, VM = 24V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
lout = 1.0 A, VDD = 5.0V
Ron (D-S) 1 Tj = 25°C, Drain-Source - 0.5 0.6
. Iout = 1.0 A, VDD = 5.0V
Output Transistor Ron (S-D)1 Tj = 25°C, Source-Drain - 0.5 0.6
Drain-Source 1 I 1.0A VDD 5V n
- . out = . ' = ' -
On Resistance Ron (D-S) 2 Tj = 105°C, Drain-Source 0.6 0.75
Iout =1.0A,VDD = 5V,
Ron (S-D) 2 Tj = 105°C, Source-Drain 0.6 0.75
ELECTRICAL CHARACTERISTICS 2 (unless otherwise specified, Ta = 25°C, VDD = 5V, VM = 24V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
VM = 24V, VDD = 5V, VDD
Vref Input Voltage Vref 11 AtTtT = H, Output on 2 - - 1.0 V
RESET = H, Output off
Vref Input Current Iref 11 VM = 24V, VDD = 5V, 0 - 100 PA
Vref = 3.0V
V 1/M=24V,VDD=5V,
Vref Attenuation Ratio ref 5 RESET = H, Output on, 1/4.9 1/5.1 1/5.3 -
(GAIN) Vref = 2.0--VDD - 1.0V
TSD Tem erature TjTSD 14 V - 5V V - 24V 130 170 ''C
p (Note) DD - ' M -
TSD Return . . - o TjTSD C)
Temperature Difference ATJTSD 14 TPTD - 130 170 C - -20 - C
VDD Return Voltage VDDR 12 VM = 24 v, RESET = H 2 - 4 v
VM Return Voltage VMR 13 VDD = 5V, RESET = H 2 - 4 v
(Note) Thermal Shut Down (TSD) circuit
When the IC junction temperature reaches the specified value, the TSD circuit turns
off the output block for both unit (AB and CD).
The data latched at that time are held without change.
The TSD circuit operates in a range from 130 to 170°C. The circuit halts operation of
the output circuits until the temperature drops by 20°C (typical) from the temperature
at which the TSD circuit started operation.
1999-03-09 13/56
TOSHIBA TB62200AF
ELECTRICAL CHARACTERISTICS 3 (Ta = 25°C, VDD = 5V, VM = 24V, lout = 0.9 A)
CHARACTERISTIC SYMBOL TCEIET TEST CONDITION MIN. TYP. MAX. UNIT
" = 90 (816) - 100 -
" = 84 (815) - 100 -
" = 79 (614) 93 98 -
" = 73 (I913) 91 96 -
" = 68 (812) 87 92 97
" = 62 (611) 83 88 93
" = 56 (810) 78 83 88
" = 51 ((99) 72 77 82
Chopper Current Vector - " = 45 (88) - 66 71 76 %
" = 40 (87) 58 63 68
" = 34 (56) 51 56 61
" = 28(85) 42 47 52
" = 23 (84) 33 38 43
" = 17(83) 24 29 34
" = 11 (62) 15 20 25
" = 6 (81) 5 10 15
" = 0 (eo) - 0 -
ELECTRICAL CHARACTERISTICS 4 (unless otherwise specified, Ta = 25°C, VDD = 5V, VM = 24V)
CHARACTERISTIC SYMBOL 25121- TEST CONDITION MIN. TYP. MAX. UNIT
t?=16/16-15/16 - o -
/?=15/16-14/16 - 11 -
/?=14/16-13/16 - 14 -
t?=13/16-12/16 - 19 -
/?=12/16-11/16 - 25 -
8=11/16-10/16 - 30 -
/?=10/16-9/16 Vref=3-0V - 34 -
Reference Voltage AVRS - t? = 9/16 - 8/16 Vref (gain) - 39 - mV
t?=8/16-7/16 =1/5.1 - 43 -
t?=7/16-6/16 - 46 -
t?=6/16-5/16 - 50 -
t?=5/16-4/16 - 52 -
6:4/16-3/16 - 54 -
/?=3/16-2/16 - 56 -
f?=2/16-1/16 - 57 -
/?=1/16-0/16 - 58 -
1999-03-09 14/56
TOSHIBA TB62200AF
AC CHARACTERISTICS
(Ta = 25°C, VM = 24 V, VDD = 5V, output load condition of 6.8mH/5.7 Q)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clock Frequency fCLK 15 - 1.0 - 25 MHz
t 40 - -
Minimum Clock Pulse tw(CLK) 15 See Fi re 1 20 ns
width wp(CLK) gu . - -
twn (CLK) 20 - -
t 40 - -
Minimum STROBE Pulse tSTROBE 15 See Fi ure 1 20 ns
Width STROBE (H) g .
tSTROBE (L) 20 - -
. tsuCLK-SIN . 20 - -
Data Setu Time 15 See Fi ure 1. ns
p tsuST-CLK g 20 - -
t - 20 - -
Data Hold Time hCLK SIN 15 See Figure l. ns
thCLK-ST 20 - -
OSC-Charge - 600 -
Delay C 1000 pF R 12 kn
. . osc = ' osc =
ft2"" Switching Delay OSC-FAST 16 fchop = 100 kHz, Iout = 0.9A ns
Delay(Slow See Figure 2. - 300 -
Decay Mode)
tr Output Load; 6.8 mH / 5.7 n - 70 -
. tf See Figure l. - 50 -
Output Transistor .
Switching Characteristic tpLH(ST) 17 STROBE(-)--OUT time - 300 - ns
Output Load; 6.8 mH/5.7 Q
tpHLST) See Figure 1. - 150 -
Noise Rejection Dead Iout = 0.9 A, fchop = 100 kHz
Band Time tBRNK 18 cosc = 1000 pF, Rosc = 12 kn 150 180 250 ns
Maximum Cho in V = 24V, V = 5V,
pp g fchop(MAX) M . DD - - 150
Frequency 9 Output active (lout = 0.9 A)
Minimum Chopping Step fixed, Ccp1 = 0.47 pF,
Frequency fchopomN) Ccp2 = 0.02 pF 32 - - kHz
. C =1000pF R = 12 k0
h F f OSC . I osc - 1 -
C oppmg requency chop 9 Output active (lout = 0.9 A) 00
. . VIVI=24V,VDD=5V,
(j:',,',','')',",.'), hTZ'IZTEEUIa' Hchop IO Iout = 0.9 A, fchop = 100 kHz - - 100 mA
g Mixed Decay Mode
Ccp1 = 0.47/1F,
. . Ccp2 = 0.02/1F,
Charge Pump Rise Time tONG 19 VM = 24V, VDD = 5V, - 1 2 ms
RESET = L-o H
TOSHIBA TB62200AF
I A-sou,
i' tsuST-CLK g
thST-CLK : : :
twn (CLK) twp (CLK)
: -ti-'r- tSTROBE (H)
i _ tsTRope (L)
. 'i-i--,", tSTROBE
tvi-sm-r.'.:- thcyc-sm
-50%"X"'DATA1S X50% I DATAO I
5 tgHL gm 5
OUTPUT
Voltage A
tpLH (ST)
OUTPUT
Voltage A
Figure 1 Test Waveforms (Timing Waveforms and Names)
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TOSHIBA TB62200AF
OSC-Charge Delay
OSC-Fast Delay OSC-Charge Delay
OUTPUT
Voltage A
OUTPUT
Voltage A
Set current _------------
OUTPUT
Current
(Slow Decay Mode)
Figure 2 Test Waveforms (Timing Waveforms and Names)
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TOSHIBA TB62200AF
OSC waveforms and output waveform timings
OSC waveform OSC (H)
EI- ----------------------------_-__--
E2- ---------------------
TOSC = 1 cycle
____._L___—————————_ L
._____-_.___________
Slow Decay mode waveform
Tosc (H) : Tosc (L)
4_____J__________-L________
Set current value - ----------------e-----
_& ______________4_J__
Slow Decay Mode : Mode changes from Charge-ssl-Fast.
In Charge mode, output starts. In Slow mode, output gradually attenuates.
In Fast mode, current is attenuated, dropping output instantly.
The output fall time is determined by the OSC signal fall time.
In Slow Decay mode, the advantage is that current ripple is small but
attenuation capability is low. The mode is used to increase current (sine
wave 0° to 90°) or to stabilize current (stabilize motor rotor).
Mixed Decay Mode : Mode changes from Charge-mst-iw.
Mode changes from Fast to Slow at 40% or 74% of the OSC cycle.
In Mixed Decay mode, current ripple is large but attenuation capability is
high. The mode is used to attenuate current (sine wave 90° to 180°) or
when current is unstable in Slow Decay mode.
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TOSHIBA TB62200AF
TEST CIRCUIT (A/B unit only. C/D unit conforms to A/B unit.)
l. VIN(H): VIN(L): 'IN(H): liN(L), IDD1, IDD2
32:9: V fAB 9
£3? 9 CR AB re -l,-s;
mU-ll iSGND
<8 SGND VMA 36
U ll RRSA M RREIA'A
(ii) 27 VDD
IDD1, [DD2
ov I f _ , Q STROBE AB
i1fLrLrLruy---o-dyco:Ai,
31:13:33]]:H - 29 DATAAB
Vary VIN. I RRSB 3 (th
o VMB 1
'IN(H): 'lN(L) Cd I 'tii,
o <29 WET SGND
it Ccp C Q
g . Ccp 2
No reset at testing Ccp B Cut) L E
SN] -- RESET
> Ccp A o
VDD-. m c 1
SGND ll . cp
Test method
VIN (H) : Set RESET to High and vary the logic input voltage from 0 to 7V.
Monitor IDD and measure the change point (VM = 24V).
VIN (L) : Set RESET to High and vary the logic input voltage from 5 to 0V.
Monitor IDD and measure the change point.
IIN (H) : Set RESET to High, set the the logic input voltage to 5V, and measure the input
current.
IDD1 : Apply VDD, input RESET, and measure IDD.
IDD2 : Input 6.25 MHz clock and measure the current when the logic is operating. Set output
to OPEN.
Setup data
DATA H 0 1 2 3 4 5 6 9 10 11 12 13 14 15
H ------------------------------------ -
STROBE Fl
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TOSHIBA TB62200AF
2. IOB, lou, IOL (A/B unit only. C/D unit conforms to A/B unit.)
............. Ci)-------
ov I f 9 STROBE AB G) IOH, IOL
ii//fLrLrLru(31ytva/us l
- SGND
s-xr-es) RESET
f' IOL
J Ccp 2
No reset at testing N
L slv1= RESET
VDD J m Ccp 1
SGND .
Test method
IOH : With VM = 24V, VDD = 5V, and logic input all = 0 applied, set RESET
output pins to GND, and measure the supply current.
H, connect the
'OB : With VM = 24V, VDD = 5V, and logic input all = 0 applied, set RESET - H, connect the
output pins to VM, and measure the supply current.
IOL : With VM = 24V, VDD = 5V, and logic input all = 0 applied, set RESET
output pins to GND, and measure the supply current.
L, connect the
Setup data
DATA 0123456789101112131415
H ----------------------_------------------------_------ -
STROBE Fl
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TOSHIBA TB62200AF
3. IMI, IM2 (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
il I f QSTROBEAB
iy/rLrLrLru(t0)tv;/us
"-(i8) RESET SGND (is
> f Ccp C Clio"
ml Ccp 2
Ccp B - Ft
At IMI testing : RESET = L (0 V) N
L At lM2 testing : RESET = H (5 V) Ccp A o
VDD [I i,',' Ccp 1
SGND .
Test method
IMI : Set the logic block to non-active (DATA = all 0), VDD = 5V, VM = 24 V, and output to open.
Measure the current input from VM supply. RESET = L
lM2 : Set the logic block only to active (CLK = 6.25 MHz), VM = 24 V, and output to open. Measure
the current input from VM supply. RESET = H
Setup data
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H ----------------------_---------------------__---_------ -
STROBE Fl
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TOSHIBA
4. |M3 (A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB R
1000pF
o«n o
<< << <<
TB62200AF
tl-:,,
No reset at testing
-L > 5 [v] = RESET
VDD Ln
Setup data
DATA L ......... X2 ....... 1 ........2. ....... 3. ....... (l ....... 1 ....... 1 ....... I J(Ekr...e....y. ...... 1 ..2 ...... 1 , ...... HXEX .............
STROBE ---------------------------------- IT"
Test method Set output to open, change phase data from 1-90-al -90 and perform switching.
When testing, input phase data at double the chopping frequency
(if fchop = 100 kHz, fDATA = 200 kHz) and measure the current value of VM supply.
Mode changes three
VM VM times in one chopping
cycle.
RRS RRS
E i Chopping cycle
a i i m
i-Ex tzou-2 ice: xa& -, .211 05. H
: OFF OFF : : Four transistors
Switch b h dat 5 1* EMMQH H
- - WI C es ase a a - A
. Imp i y p 5 amp i OFF OFF
1 L d .' .' L d : Charge Fast
L1 T 0a T L2 L1 T oa I L2 l Two transistors
--'a1EE . i EW"- --'a1EE . i a switching
OFF i i i OFF OFF OFF
i . i i Two transistors switching -, "
Two transistors switching -
V ' _ ' _ F-
I Four tranSIstors switching In one cycle I
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TOSHIBA TB62200AF
5. VRS(H--L), Vref(GAIN) (when measuring phase A) after measurement
(A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
AILSGND
VMA 36
RRSA Cali
3 Cai?,
ov I f 9 STROBE AB r-CD-o
5V B e Oscilloscope
0V|1ll|l|1®CLKAB
E Ci", j,
VM B 0 Vary between 0 and IN-i-
(FIN) SGND
H3) RESET
> i CcpC Clio"
J Ccp 2
No reset at testing p Cut) i-i,?,
s NI = RESET
L Ccp A o u.
- > ti.
VDD J Ln 't Ccp 1
SGND J:,';
VRS(H~L) : Input torque data = 100% (HH) and vary the voltage between VM and RS pins.
Measure the voltage (VRS) when output changes from fixed Charge mode to
another mode.
Also measure VRS when torque data = 85% (HL), 70% (LH), or 50% (LL) as above
and calculate the ratio using VRS value at 100% as reference.
VRs(*)
1/ref(GAIN) : Vref(GAlN) = (*VRS : when torque data = 100%)
Setup data
STROBE I I
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TOSHIBA TB62200AF
6. Aloutl, A'outZ (A/B unit only. C/D unit conforms to A/B unit.)
:g‘ Vref AB 9 l
as T." F, CR AB l a
I SGND
g g) VM A 36
RRSA 34 RRSA
27 VDD A
Monitors current
5 V E waveform.
ov I f CE STROBE AB
5V FLrlrLru
ov C3ii CLK AB -
33 1:133:33]: 29 DATA AB
RRS B 3 R‘RS B
s-es) RESET
> i Ccp C Q
Ccp B >
No reset at testing Cd, L:
5 NI = RESET CP,
Ccp A u.
V -- > Q,
DD J m Q Ccp 1
SGND J 0.
With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and
measure the various output currents at constant current (@0.9 A) operation.
Setup data
DATA 0 1 2 N 3 I 4 5 6 7 8 9 k10/ 11 12 13 14 15
L .........................................................................................................
H ----------------------_--------_--------------__----_----- -
STROBE Fl
0% 40% 60% 100% 0% 40% 60%
Output current value
(set current value) I
Charge fast
a Slow
Charge
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TOSHIBA TB62200AF
7. IRS (A unit only. B/C/D unit conforms to A unit.)
When measuring phase A
£3 T7 F, CR AB L,
tXI I J J SGND
< 8 SGND
27 VDD
CE STROBE AB
'pg" CLK AB
29 DATA AB
- SGND
-iii.i RESET
RESET- = L up 2
VDD L” Ccp 1
SGND .
With L input to RESET, connect VM and RRS to the power supply, and measure the current input
to the Rs pin. (Either drop all the input pins to GND level or input all Low data to the DATA
pin, then perform measurement. At that time, leave all other output pins open.)
Setup data
DATA 01
H -------------------------------- IT"
STROBE
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TOSHIBA TB62200AF
8. RON(D-S), RON (S-D) when measuring output A (A unit only. B/C/D unit conforms to A unit.)
Vref AB 9
VMA 36
RRSA 34
ov I f Ci?, STROBE AB
Curve tracer
gxllllllll @CLKAB
Curve tracer
s-xr-es) RESET
l l Ccp 2
No reset at testing C',',
SW] = RESET
Ps Ccp 1
SGND er"
Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between
VM and OUT when 'OUT = 1000 mA or the voltage between OUT and GND. Then, change the
phase and repeat measurement. At that time, leave the output pins which are not measured
Setup data (Vary the phase data during testing.)
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H ---------------_---------------------------------- -
STROBE Fl
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TOSHIBA TB62200AF
9. fchop (fchop(Min), fchop(Max)) (A/B unit only. C/D unit conforms to A/B unit.)
Oscilloscope
8 8 CRAB L,
n: __/ ll tYO
m/ SGND
< m SGND
27 VDD
Car" STROBE AB
Cao) CLK AB
29 DATA AB
ZBDFSET
Change the Rosc and Cosc values and measure the frequency on the CR pin using the
oscilloscope.
Oscilloscope waveform (example)
______L_____
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TOSHIBA TB62200AF
10. Hchop (Triangular wave high value) (A/B unit only. C/D unit conforms to A/B unit.)
yi: Vref AB 9
.n N l
as F." F, CR AB a
g 3/1 J SGND
08 SGND VMA 36
RRSA 34 R
27 VDD A
- - Monitor current
A waveform.
ov I f CE STROBE AB
ov C3ii CLK AB -
RRSB 3 RRSB
s-es) RESET
> i Ccp C Q
Ccp B >
No reset at testing CE, J_:
5 NI = RESET
Ccp A o u.
VDD m L}- Ccp 1
SGND J
With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and
measure the current ripple width (Hchop) at constant current (@0.9 A) operation. Input
Iout = 0.9 A.
Setup data
DATA 0 1 2 N 3 I 4 5 6 7 8 9 \10’ 11 12 13 14 15
L .........................................................................................................
STROBE
0% 40% 60% 100% 0% 40% 60%
Reference voltage
Charge Fast
Hchop Slow
Charge
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TOSHIBA
TB62200AF
11. Vref, Iref (A/B unit only. C/D unit conforms to A/B unit.)
Oscilloscope
* When measuring Iref, fix
Vref = 3 V and measure.
@CR AB
Q STROBE AB
Cid, CLK AB
29 DATA AB
No reset at testing
5 [V] = RESET
VDD - m
Monitor
* Vary Vref = 2 to VDD - 1.0V SGND
Vref AB
Vref : Vary Vref = 2 to VDD - 1.0V and confirm that output is on.
Iref : When VM = 24V and VDD = 5V, apply the specified voltage of 3V to the Vref and
monitor the current flow value.
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TOSHIBA TB62200AF
12. VDDR (A/B unit only. C/D unit conforms to A/B unit.)
Oscilloscope
J :GND
ov I f ®STROBEAB
'l/FIU-lil-.
0V @CLKAB
s-iii) RESET SGND
No reset at testing VM “N
5 [V] = RESET J
VDD Vary from 0V.
SGND ,
Monitor the output pins. Increase the VDD voltage from 0. Measure the VDD value when output
starts.
Next, decrease the VDD voltage and measure the VDD value when output stops.
Setup data
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H ---------------------------------- -
STROBE Fl
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TOSHIBA TB62200AF
13. VMR (A/B unit only. C/D unit conforms to A/B unit.)
Oscilloscope
J :GND
ov LI ®STROBEAB
gxllllllll @CLKAB
SV - 29 DATA AB
s-iii) RESET SGND
No reset at testing Vary from 0V. -/
5 [V] = RESET l
VDD - i
With the CLK signal and DATA (all High) input, increase the VM voltage from 0.
Measure the VM value when output starts.
Next, decrease the VM voltage and measure the VM value when output stops.
Setup data
H -------------------------------- -
STROBE Fl
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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TOSHIBA TB62200AF
14. TjTSD, ATjTSD (Measure in an environment such as an constant temperature chamber where the
temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9 J,
VMA 36
RRSA M
5V Cfs?
ou I f Q STROBE AB
B Ci? Curve tracer
0V|1Il|l|1®CLKAB -
RRSB 3 "
_ -GND VM B 1 l
Curve tracer
(FIN) SGND
.s-(2is) RESET
> Ccp C @
l Ccp 2
Ccp B >
No reset at testing @ J_ir:
5 NI = RESET
Ccp A o u,
>-- ti,
ll 3 Ccp 1
SGND c;
TjTSD : Increase the ambient temperature. Measure the temperature when output stops.
ATjTSD : Gradually decrease the temperature from that when the TSD circuit is turned off
(output off). Measure the temperature when output restarts.
Setup data (Vary the phase data during testing.)
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H ----------------------_----------------------_---_------ -
STROBE I I
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TOSHIBA TB62200AF
15. fCLK. tw(CLK). twp (CLK), twn (CLK), tSTROBE, tSTROBE (H), tSTOBE (L),
tsuCLK-SIN, tsuST-CLK, thCLK-SIN, thCLK-ST (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
9 CR AB _L;
ILSGND
Cosc AB R
1000pF
V If @STROBEAB
3¥|1|1|1|1@CLKAB
RRSB 3
-GND VMB 1
No reset at testing
s NI = RESET
SGND J
Input any data at fCLK (max), perform chopping, and monitor the output waveform.
For the measuring points, see the timing chart below.
0.47#F
Setup data
DATA 0 1 2 N 3 I 4 5 6 7 8 9 \10’ 11 12 13 14 15
L .........................................................................................................
H ----------------------_----------------------_---_------ -
STROBE Fl
Measuring points
tw (CLK) .
CLK i E .
I ..S..50% / ~ ..... _
i tsuST-CLK g
I -r:_-tsrRossE(H)
":'"':. tSTROBE (L)
i r—i tSTROBE
tsuCLK-SIN -n-":"- tthK-SINE
--- . .
thST-CLK _.-.'-,
twn (:CLK) . twp (:CLK)
DATA 50%"X"'DATA1S ”X-gm I DATAO I
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TOSHIBA TB62200AF
16. OSC-Fast Delay, OSC-Charge Delay (A/B unit only. C/D unit conforms to A/B unit.)
Monitor Monitor
f i 0 CR AB -l,-s,,
ttt ”dl iSGND
< o SGND
k) ll AAA
27 VDD
5 v - UWJ
OV CE STROBE AB
0V|1ll|l|1®CLKAB
SV 29 DATA AB
s-x-fir) RESET
No reset at testing a
5 NI = RESET
VDD Ln
SGND J
Fix the output current value in Slow Decay mode and turn the output on. Measure the time
until the output switches from the CR pin waveform and the output voltage waveform.
Setup data
DATA 01
STROBE
Bottom
F--.-'.. Osc-Charge Delay
Osc-Fast Delay "ir--.:
of-soon E
VoutA - N 50%
Charge
(Mode) i Charge ; Slow i' Fast
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TOSHIBA TB62200AF
17. tpHL(ST), tpLH (ST), tr, tf (A/B unit only. C/D unit conforms to A/B unit.)
Monitor
RL=5.7Q
OV u QSTROBEAB
0v|1ll|l|1®CLKAB -L=6.8mH
SV 29 DATA AB
a..-(2is) WI" SGND
No reset at testing --:r.
5 [V] = RESET
VDD - E
Setup data
DATA X0 1 2 3 4 5 6 7‘9 1011 12 13 MEX
L ........................................................................ - _................-.....................-.............
H ----------------------_----------------------_---_------ -
STROBE fl
Switch PHASE every 130 gs and measure the output pin voltage and the STROBE signal.
(Oscilloscope waveform (example))
5 130prs 5
50%”..l.“ l 50% .... 'l. ... \
E tEHL (ST) E
OUTPUT : .
Voltage A E _.. i..., 50%
tpLH (ST)
OUTPUT
Voltage A
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TOSHIBA TB62200AF
18. tBRANK (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
Vref AB it
J SGND
a Cab" Monitor
ov I f CE STROBE AB
ollllllll @CLKAB -
Ms B Ci]
-GND VM B T,
yss (ri)-
(Fm) '
- Pulse
.ar-) RE ET
28> s generator
> i Ccp C Cleo"
Ccp B >
No reset at testing ‘I! E
5 NI = RESET f,
Ccp A o
VDD 1m
SGND J
tBRANK is the dead time band for avoiding malfunction caused by noise. Apply sufficient
differential voltage (when Vref = 3V, 0.6V or higher) to VM-Rs and apply duty. When the pulse
width reaches a certain value, triggering feedback and changing the output. Check the value.
Rs pin voltage ..... ' m.." -
Apply pulse to the Rs
pin so that the Rs pin
= VM voltage - 1.0V.
Measure the pulse width
where output changes.
Setup data
DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H ---------------------------------------------- -
STROBE Fl
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TOSHIBA
TB62200AF
tONG (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
Ci? CR AB L,
Vref Aui'im,
VMA 36
RRSA 34
27 VDD A Q
a Cab'
Ci?, STROBE AB
Cad, CLK AB
29 DATA AB
RRSB 3
- -GND VMB 1
(FIN) :: SGND
SV a) RESET
0V ___________ Ccp C Cii"
OFF-yon Ccp 2
Ccp B -t-t
Ccp A 0 I 9 Monitor
VDD -- it ’3
SGND la:
Ccp 1 0
Apply VM and VDD and change RESET from L to H.
Measure the time until the CcpA pin becomes VM + VDD x 90%.
VDD + VM .............. : ............................................................... :' ..............
VM + (VDD X 90%) .............. i ............................................................ . .....................................
VM i .............................................................. i." ......................................
5 v ............. '..
RESET 50% .
0 V __/: _.----------------------------
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TOSHIBA TB62200AF
PD-Ta (Package power dissipation)
POWER DISSIPATION PD (W)
25 50 75 100 125 150
AMBIENT TEMPERATURE Ta (°C)
Rth (j-a) IC only(96''C/W)
When mounted on the board (38.1°C/W)
Board size (90 x 230 x 1.6mm)
)k. Rth (j-c) : 8.5°C/W
How to calculate set current value
The set current value is calculated according to RRS and Vref.
Torque
I (Max) = V (GAIN) x V (V) x -
out ref ref (RRS + RIC)
Vref (GAIN) = 1/5.1, RIC (wiring resistance in IC) = 0.04 (Q)
(Example)
Vref = 3 (V)
Torque = 100 (%)
To output lout = 0.8 (A),
0.8 A = - x 3 V x -
( ) 5.1 ( ) RRS + 0.04 (n)
RRS = 0.695 (n) (0.5W or higher) is required.
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TOSHIBA TB62200AF
Output transistor operating mode
VM VIVI VM
RRSSE RRS I giRRs
V Rs pin Y Y RS 'pin V J Y Rs pin 7
LE t t aaou-2 LE t t aou-2 i- i t amu-2
5 (Note) g OFF OFF i." (Note) i." OFF OFF i' (Note) i'
4 mm 4 4 m 4 4 m 4
L-1ezfLoadfs/s LE?Load?§pLi L_“E?Load?§li
OFF .3 3 ON 3 2 ON i i OFF
: . i - c' . i W TI . j.
iPGND yd I lPGND
Slow mode Fast mode
Charge mode
(Remark) In Mixed Decay mode, mode changes from Fast to Slow at 40 or 74% of 1 fchop
cycle after charging is complete in Charge mode.
(Note) Although there are parasitic diodes on the dotted lines, they are not normally used
in this IC.
Output transistor operation functions
CLK U1 U2 L1 L2
Charge ON OFF OFF ON
Slow OFF OFF ON ON
Fast OFF ON ON OFF
(Note) The above table is an example where current flows in the direction of the arrows in
the above figures.
When the current flows in the opposite direction of the arrows, see the table below.
TOSHIBA TB62200AF
Current modes
O Sine wave in increasing (Slow Decay mode normally used)
.' Slow
Set current 5 Slow
value 3 f j / a
Fast Charge Fast
Slow i'
Set current Slow i Charge
value / -, / a i
Charge Fast Charge Fast 5
C) Sine wave in decreasing (Mixed Decay mode normally used)
Set current Fast Because current attenuates so quickly, the current immediately
value A A follows the set current value.
Charge
Slow Charge Fast
Set current
Charge
C) Sine wave in decreasing (Slow Decay mode normally used at attenuation)
Because current attenuates slowly, it takes a long time for
the current to follow the set current value (or the current
Slow does not follow).
Selt current yr Slow
va ue r''""'""-------.,.,
Fast F t\/ Slow F t t:C'f""""""""""-s-ci:-r----,
as as ow
Charge Fast
Charge Charge
Charge
Set current
(Note) The above charts are schematics. The actual current transient responses are curves.
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TOSHIBA TB62200AF
Operation in Slow Decay mode
tdelay tdelay
Reference
voltage
Charge :..' Charge
:.' fast :.' fast
CR (Osc) waveform
t fast ; t fast
Flow chart
Using the oscillator waveform on the CR pin for chopping, Slow
Decay mode is generated. l
Charge
In Slow Decay mode, current chopping is performed in the flow
chart shown on the right. _iis"re",ti,c,'j,sr,
Teye curren
In Slow Decay mode, Fast mode continues as long as the feedback ' Z Ire
time delay (tdelay) for current comparison (from detection of motor
current exceeding the reference current to output changed to Decay owlecay
mode) and pulls up the current to the set current value. Start discharging
Fast mode duration can be set by combining external capacitors on CR 'l"
the CR pin.
Fast Decay
Start charging
CR signal
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TOSHIBA TB62200AF
IC power dissipation
IC power dissipation is classified into two : power consumed by transistors in the output block and
power consumed by the logic block and the charge pump circuit.
0 Power consumed by the output block (calculated with Ron = 0.6 Q)
In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and
lower transistors of the H bridges. The following expression expresses the power consumed by the
transistors of a H bridge.
P (out) = (upper Tr + lower Tr) x Iout (A) x VDS (V) = 2x(lout)2 x Ron ....... (1)
The average power dissipation for output under 4-bit micro step operation (phase difference
between phases A and B is 90°) is determined by expression (1).
Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.
lout(Peak) = 0.9A
VM = 24V
VDD = 5V
P (0.9 A) = 0.97 (W) w........................................................ (2)
0 Power consumed by the logic block and IM
The following standard values are used as power dissipation of the logic block and IM at operation.
I (LOGIC) = 4mA (Typ.)
I (IM3) = 15mA (Typ.) (because of two units, 30/2 = 15mA)
The logic block is connected to VDD (5V). IM (total of current consumed by the circuits connected
to VM and current consumed by output switching) is connected to VM (24 V). Power dissipation is
calculated as follows :
P (Logic & IM)= 5 (V) x 0.004 (A) + 24 (V) x 0.015 (A) ....................... (3)
= 0.38 (W)
Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.
P = P (out) + P (Logic & IM) = 1.35 (W)
Power dissipation when output current is 0.6A is determined in the same way :
P (0.6 A) = P (out) + P (Logic & IM)
= 0.81 (W)
Power dissipation for 1 unit at standby is determined as follows :
P (standby) = 24 (V) x 0.015 (A) + 5 (V) x 0.004 (A)
= 0.38 (W)
Power dissipation when Motor A = 100%, Motor B = 40%, P (TOTAL), is determined as follows :
P (TOTAL) = P (Motor A OUT) x 100 (%) Duty + P (Motor BOUT) x 60 (%) Duty
0.81 (W) X 100 (%) + 1.35 (W) x 40 (%) + 0.38 (W) x 60 (%)
1.58 (W)
For thermal design on the board, evaluate by mounting the IC.
1999-03-09 42/56
TOSHIBA TB62200AF
Power supply sequence (recommended)
VDD(Min)
VDD) VDDR-IIIIII
VM(Min)
VMR ---
Internal
RESET -
INPUT RESET
H -.-.-
I I I I
t0N6 tONG
Takes up to tONG until operable.
. Non-operable area
(Note 1) When the VDD value drops to VDDR or below, to avoid malfunction, the IC is
internally reset. Likewise, when the VM value drops to VMR or below, the IC is
internally reset. To avoid malfunction, when turning on VM or VDD, we
recommend you input the RESET signal at the above timing.
It takes time for the output control charge pump circuit to stabilize. Wait up to
tONG time after power on before driving the motors.
(Note 2) When the VM value is between 3.3 to 5.5V, the internal reset is released, thus
output may be on. In such a case, the charge pump cannot drive stably because of
insufficient voltage. We recommend the RESET state be maintained until VM
reaches 20V or more.
(Note 3) Since VDD = 0V and VM = voltage within the rating are applied, output is turned
off by internal reset. At that time, a current of several mA flows due to the bus
between VM and VDD.
1999-03-09 43/56
TOSHIBA TB62200AF
Relationship between VM and VH
VM - VH (& Vcharge UP)
VH voltage
VDD = 5V
Ccp1 = 047/11:
3 Input RESET. Ccp2 = (h02pF
(RESET = 0 V)
VM voltage
tin 30V
Usable area
VH VOLTAGE, CHARGE UP VOLTAGE,
VM VOLTAGE (V)
Charge up voltage
0 2 4 6 81012141618202224262830
SUPPLY VOLTAGE VM (V)
(Note) To prevent faulty operation, stop the output circuit by inputting 0000 to the current
data when VM voltage is lower than the regulated voltage (20--30 V).
When output circuit is stropped, VM can fluctuate between 0V to the regulated
voltage (20--30 V).
Charge up pump rise time
tONG :
VDD + VM ................ '.." R............................................................ i' .............................................
VM + (VDD X 90%) ................ z _........................................................... i ........................................
tONG is the time required after releasing reset until the Ccp2 capacitor (capacitor used to
absorb charge) charges Ccp1 (capacitor used to save charge) to the VM + VDD voltage.
Until the Ccp1 voltage reaches the VM + VDD voltage, the internal circuits cannot drive
gates properly. Be sure to drive the motors at least tONG.
The Ccp1 capacitance can be increased. Reducing the Ccp1 capacitance shortens initial
charge-up time but increases voltage fluctuation.
Depending on the combination of capacitors (especially if the Ccp2 capacitance is small),
the voltage may not be sufficiently boosted. Toshiba recommends the following
combination of capacitors :
Recommended capacitance : Ccp1 = 0.47 (pF), Ccp2 = 0.02 (pF)
1999-03-09 44/56
TOSHIBA
External capacitors for charge pumps
TB62200AF
When VDD = 5V, fchop = 100 kHz, and L = 10 mH is driven with VM = 24 V, Iout = 900 mA, the
theoretical values for Ccp1 and Ccp2 are as shown below :
Charge pump delay time
CcpZ CAPACITANCE
Ccp1 - Ccp2
Usable area
Recommended area
1 = 0.47/11:
cp2 = 0.02 F
Ccpl CAPACITANCE (pF)
Charge pump delay time depending on set condition (tONG)
Evaluate driving under the following Clondition E . '
calculation conditions -Ccp1 = 2.2 ,u'F
VM = 27V Ccp2 = 0.0047 M'
800 VDD = 5 V
fchop = 150 kHz /
C diti A C diti B Condition C ; /
200 on non ; on Hon ; Cc 1 =0.47 F ._.
Ccp1 = 0.22 pF Ccp1 = (h33prF chz = 0.02 It.,-----"':':'?:: D ;
Ccp2 = 0082 M' Ccp2 = 0.047 M' fel = 3'31”: -
cp = . y
Condition A Condition B Condition C Condition D Condition E
(Note) Since the above values are theoretical, use our recommended conditions of
Ccp1 = 0.47 pF, Ccp2 = 0.02pF.
1999-03-09 45/56
TOSHIBA
TB62200AF
Operation of charge pump circuit
NNN VM = 24V
VDD VM
=5V Rgr\16,21,34 r 18, 19, 36
27 ll,; Q
v - CcpA
H L (P,
( I . Nev
r''''.'..'.''..''.'..'.'.''''.'. il
i I i2
EEy-iisxr-i.. Di2 x
i Dil Cch
Cy-, A' K12 u.
Tr2 V ji-
Output CD 3 'D. t
. |®_ 8 'il _ n
Comparator .............. - th ''t.
Output w fd 8 ,
H switch M
& R1 CcpC
Controller
VH = VM + VDD = charge pump voltage
i1 = charge pump current
Initial charging
i2 = gate block power dissipation
C) When RESET is released, Tr1 is turned on and Tr2 turned off. Ccp2 is charged from Ccp2 via Di1.
© Tr1 is turned off, Trit is turned on, and Ccp1 is charged
from Ccp2 via Di2.
(3) When the voltage difference between VM and VH (CcpA pin voltage = charge pump voltage)
reaches VDD or higher, operation halts (normal state).
Actual operation
© Ccp1 charge is used at fchop switching and the VH potential drops.
(h) Charges up by co and © above.
Output switching
Initial charging Normal state I
w : : E E E
o . : : : : :
< : : :
L-, s r.,-''''''''" s :\ i jr"'"''''''"""); 2
g .' .' , .' , .'
l i.l,w'''''''" s g Y a V V"
E) . I I I I
ru I :
Lu I I
U? I I
D: I I
v op © © 5(4) © ©
1999-03-09 46/56
TOSHIBA TB62200AF
OSC circuit frequency (chopping frequency)
OSC circuit equivalent
+ Comp1
Tosc signal
Mixed Decay signal
To signal
E1 ----------_----__---
__._________L_
L________
E2 ----------------
The external capacitor for setting the chopping frequency (Cosc) is connected to the CR pin. It is
charged by current flowing through the external resistor Rosc (t0~t1). When the voltage becomes
E1 = VDD x (R1 + R2)/(Ro + R1 + R2) (V), Comp2 output is turned on, triggering Tr1 via the FF circuit.
This attenuates the charged current from capacitor Cosc (t1--t2).
When the potential of the CR pin drops to E2 = VDD x R2/ (R0 + R1 + R2) (V), Comp1 is turned on,
turning off the Trl via the FF circuit (Cosc is charged). Repeating this generates a saw-tooth waveform.
The relationship between capacitance Cosc and resistance Rosc is expressed as follows :
T (s) = t1 + t2 = 0.7 X Cosc (F) X Rose (Q) + 616 X Cos: (F)
1999-03-09 47/56
TOSHIBA TB62200AF
CR (OSC) frequency setting
0 When the external capacitor (Cosc) connected to the CR pin is fixed to 1000pF, the chopping
frequency obtained by varying the Rosc value is as shown below:
CR BLOCK RESISTANCE (Rosc) - fchop
condition
VM = 24V
120 VDD = 5V
Cosc = 1000 pF
fchop (kHz)
0 10 20 30 40 50
CR EXTERNAL RESISTANCE (Rosc) (m)
OSC frequency setting
Where the cycle is T (s), the following equation expresses the cycle.
When Rosc = 13 (k0), Cosc = 1000 (pF), Te. 9.7 (ps). The chopping frequency fchop is determined as
follows :
fchop =1/T =1/9.7 x IO-ti-e, 103 (kHz)
1999-03-09 48/56
TOSHIBA TB62200AF
Application operation input data (example : 2-Phase Excitation mode)
T°R§UETOR1QUE MDM B DEEAY Bo B1 B2 B3 PHASE B MDM A "fy' A0 A1 A2 A3 PHASE A
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1
2 1 1 0 0 1 1 1 1 0 0 O 1 1 1 1 1
3 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 O
4 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the
STROBE signal.
For the input conditions, see page 9, Functions.
We recommend Mixed Decay mode (40%) as Decay mode. Set torque to 100%.
Output current waveform of 2-phase excitation sine wave
20 Phase B
(Note) 2-phase excitation drive usable only in Mixed Decay mode.
2-phase excitation drive in Slow Decay mode is prohibited. Don't use it.
1999-03-09 49/56
TOSHIBA TB62200AF
Application operation input data (example : 1-2 Phase Excitation mode)
TOR8UET°R1QUE MDM B DEEAY Bo B1 Bit B3 PHASE B MDM A DEgAY A0 A1 A2 A3 PHASE A
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 o o 1 1 1 1 1 o o o o o o 1
2 1 1 o o o o o 1 1 o o o o o 1 1
3 1 1 o o o o o o 1 o o 1 1 1 1 1
4 1 1 o o o o o 1 o o o o o o 1 1
5 1 1 o o 1 1 1 1 o o o o o o o o
6 1 1 o o o o o 1 o o o o o o 1 o
7 1 1 o o o o o o o o o 1 1 1 1 o
8 1 1 o o o o o 1 1 o o o o o 1 o
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the
STROBE signal.
For the input conditions, see page 9, Functions.
We recommend Mixed Decay mode (40%) as Decay mode. Set torque to 100%.
Output current waveform of 1-2 phase excitation sine wave
100 %)
- 38 Phase B
(Note) We recommend 1-2 phase excitation drive in Mixed Decay mode.
1999-03-09 50/56
TB62200AF
TOSHIBA
Application operation input data (example: 4-bit micro steps)
11 12 13 14
0 0 0 0
0 0 0 0
4 5 6 7
0 0 0 0
0 0 0 0
MDM B DEEAY Bo B1 B2 B3 PHASE B MDM A DE/EAY A0 A1 A2 A3 PHASE A
TORQUETORQUE
1999-03-09 51/56
TB62200AF
TOSHIBA
B0 B1 B2 B3 PHASE B MDM A A A0 A1 A2 A3 PHASE A
MDM B DE
TORQUE TORQUE
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the
STROBE signal.
For the input conditions, see page 9, Functions.
We recommend Slow Decay mode in the ascending direction of the sine wave ; Mixed Decay mode
(40%) in the descending direction. Set torque to 100%.
1999-03-09 52/56
TOSHIBA TB62200AF
Output current waveform of pseudo sine wave (4-bit micro steps)
17 micro-step from 0 to 90° drive is possible by combining current data (AB & CD) and phase data.
For input current data at that time, see section on Current X in the list of the Functions.
We recommend Slow Decay mode when the sine wave is rising (current increasing from 0); Mixed
Decay mode (40%) when falling (current decreasing).
In Mixed Decay mode, select either 40% or 74% depending on the load.
1999-03-09 53/56
TOSHIBA TB62200AF
4-bit micro steps
Output current vector line (Standardized 1 step as 90°)
63 71 77 83 88 92 96 100
0 10 20 29 38 47 56
IB (%)
For data to be input, see the function of Current AX (BX) in the list of Functions (10 page).
1999-03-09 54/56
TOSHIBA
TB62200AF
RECOMMENDED APPLICATION CIRCUIT
The values for the devices are all recommended values. For values under each input condition, see
the above-mentioned recommended operating conditions.
(example : fchop = 100 kHz, CR : Iout = 0.6(A), LF : Iout = 0.9 (A))
Vref AB 9
g? Ccp 2
l we 0.02 ttF
(*) We recommend the user add bypass capacitors as required.
Make sure as much as possible that GND wiring has only one contact point.
Also, make sure that the VM pins are connected.
For the data to be input, see the section on the recommended input data.
6 CR AB Vref AB L, t
(*) J m g
SGND '-
VMA 36
RRSA 34 '"
RRSA 0.660
27 VDD A
ov I f CE STROBE AB
5v“ Fl n Fl STEPPING
CLK AB MOTER 1
0V Cid) (LF)
0V C:iii
RRS B 'N,
RRS B 0.6652
0 P-GND VM B
5 V CLK CD SS
ov I'LFLFLFL 43 (Fih)
5 v DATA CD
ov EEEEEEEI: $3 ch
(W LI" Ciiis? RESET Ms C 'N,
RRSC 1.0 n
5V 24 STROBE CD
ov I f C
D STEPPING
MOTER 2
g) x AAA
- m '- DCRCD RRSD100
L > t u, t
Van l m g J 'ri'
SGND SGND '- SGND u '-
.. ti, LL
o Q, >
T" 8 --sct
careful when designing output lines, VDD (VM) lines, and GND lines.
Because there may be shorts between outputs, shorts to supply, or shorts to ground, be
1999-03-09 55/56
TOSHIBA TB62200AF
OUTLINE DRAWING
HSOP36-P-450-0.65 Unit : mm
3.55i0.1
---------------_------------
12.0:02
16.5MAX
16.0i0.1
I Grl E "
- - _ "-t-'-- = _ +1; m ,J
_ rs CM
l , - CM cu d
I CII/f.',,,
a thl tf 'g""-'"'"";
Weight : 0.799 (Typ.)
1999-03-09 56/56
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