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TA8667FN/a10avaiHORIZONTAL AFC IC
TA8667PTOSN/a15avaiHORIZONTAL AFC IC
TA8667PTOSHN/a245avaiHORIZONTAL AFC IC


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TA8667F-TA8667P
HORIZONTAL AFC IC
TOSHIBA TA8667P/F
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA8667P, TA8667F
HORIZONTAL AFC IC
The TA8667P, TA8667P is generation of high-frequency TA8667P
clock synchronized with horizontal sync signal.
(The TA8667P/F is H AFC IC for TC9086F(3DYCS),
TC9097F (WAC).)
FEATURES
lt Generate of Typ. 28MHz (1820fH) clock.
DlP18-P-300-2.54D
0 Generate of vertical sync signal. TA8667F
o Generate of composite sync signal.
SSOP24-P-300-1.00B
Weight
DIP18-P-300-2.54D : 1.47g (Typ.)
BLOCK DIAGRAM SSOP24-P-300-1.00B : 0.32g (Typ.)
c.s. OUT v. Sepa OUT v. IN v. OUT
TA8667P a cu f2 (ii)
-D VCC1
V.Sea|N 1— V.Snc + .
p C y T Shaping _:15) VCC2
H.V. Sepa IN c- HN, Sync Phase Comp. - VCO Cont. - VCO - s/CIC, -D 2¢SN OUT
- - - -12 GND1
v. Mask ------ -l D
-C1js) GND2
V. Mask IN H. ref IN P.D. OUT Bias filter VCO TANK
1 2001-06-25
TOSHIBA TA8667P/F
TERMINAL CONNECTION DIAGRAM
v. Sepa IN G V Ci) GND? v. Sepa IN C V Ci? GND2
H.V. Sepa IN Ci) D VCO TANK H.V. Sepa IN C D VCO TANK
cs. our C) LL D Ci) D
v. Sepa OUT Ci; g D VCC2 C u- D
V. IN G? m D Vcc1 c.s. OUT 6: ts Ci)) VCC2
v. OUT G? 00 D 2¢5N OUT v. Sepa OUT (E to E9) Vcc1
H. ref IN C if D GND1 v. IN C : Ci) 2¢SN OUT
v. Mask IN (i2 D filter v. OUT Ci) < D GND1
PD. OUT Ci) G) Bias Ci: r- D
H. ref IN @ D
V. Mask IN 63 39 filter
P.D. OUT Ci D Bias
TERMINAL FUNCTION
TA8667P TA8667F TYP. DC
PIN No. PIN No. PIN NAME VOLTAGE I/O CIRCUIT FUNCTION
e V. Sepa IN : Inputs vertical
sync signal separated from
1 1 V. Sepa IN video signal.
(6.0V) o H.V. Sepa IN : Inputs
2 2 H.V. Sepa IN horizontal and vertical sync
it. signals separated from
i” video signal.
r . o Outputs horizontal and
3 5 CS. OUT - vertical sync signals after
CD ff, E ?_ wave shaping.
I 8 q GND1
r ir o Outputs vertical sync
4 6 V. Sepa OUT - ngnal. Horizontal sync
C) signal remains m V. Sepa
I OUT.
, GND1
TOSHIBA
TA8667P/F
TA8667P TA8667F
PIN No. PIN No. PIN NAME
TYP. DC
VOLTAGE
I/O CIRCUIT
FUNCTION
0 Inputs the signal outputted
from V. Sepa OUT after
horizontal sync signal was
removed.
- Vcc1
o Outputs wave-shaped
vertical sync signal.
H. ref IN
0 Phase Comp Input. The
reference input is the
15.7KHz signal derived
through dividing the 2/SN
OUT signal by N
(1820--2426) with an
external frequency divider
(duty : 50%).
V. Mask IN
(L : 0V)
(H : 5V)
0 Driving the V. Mask IN
signal to high turns off the
phase-comparison
operation. Inputs the signal
which masks serrated and
equalizing pulses of video
signal.
P.D. OUT
10 13 Bias
0 Connect an external filter.
TOSHIBA TA8667P/F
TA8667P TA8667F TYP. DC
PIN No. PIN No. PIN NAME VOLTAGE I/O CIRCUIT FUNCTION
11 14 filter 6V It Connects an external filter.
12 17 GND1
18 24 GND2 o Power-supply voltage and
14 19 Vcc1 GND.
15 20 Vcc2
o Outputs the stable sin
13 18 2¢SN OUT - wave of N times the fH
E frequency.
f-_--" W
16 22 5.2V C) I o 'te the ossilla’ghg . h
VCO TANC C) (,rae/dCfcyel'tye,Sf,s,tai',1htde
17 23 5.2V T T y
”7 Ar GND2
TOSHIBA
MAXIMUM RATINGS (Ta = 25°C)
TA8667P/F
CHARACTERISTIC SYMBOL RATINGS UNIT
Power Supply Voltage VCC max 12 V
Input Signal Voltage ein max 6 Vp-p
Power TA8667P 1320
. PD mW
Consumption TA8667F 830
Operating Temperature Top, -20--70 "C
Storage Temperature Tstg - 55--150 ''C
TA8667P TA8667F
A 1500 A 1500
E 1320 E
a 1000 Z 1000
E 845 f?: 830
'ii' 500 'i' 530
2 . . 2 . .
25 70 150 25 70 150
OPERATING TEMPERATURE (°C) OPERATING TEMPERATURE (°C)
RECOMMENDED OPERATING CONDITION
KIT PIN NAME MIN. TYP. MAX. UNIT
14 Vcc1
15 VCC2 8.5 9.0 9.5 V
5 2001-06-25
TOSHIBA TA8667P/F
ELECTRICAL CHARACTERISTICS (Vcc=9.0V, Ta =25°C)
All the pin numbers in the below description are those of the TA8667P.
TEST TEST CONDITION
CHARACTERISTIC SYMBOL PIN (SEE"TEST CIRCUIT") MIN. TYP. MAX. UNIT
VCC 8.1 9.0 9.9 V
Operating Power Supply
Voltage
Operating Power Supply
Current
ICC 15 27 40 mA
I) Measure Voltages V3 and V6
of Pin 3 and Pin 6, respectively.
2) Connect variable voltage
VOH (1) 3 ' 6 source to Pin 2 and Pin 5. 2.5 4.0 5.5
3) Change variable voltage
source and measure voltages
High Level V3 and V6 when high.
1) Measure Voltage V4 of Pin 4.
2) Connect variable voltage
source to Pin 1.
VOH (2) 4 3) Change variable voltage 7.0 - 8.3
source and measure voltage
Output V4 when high.
Voltage 1) Measure Voltages V3 and V6
of Pin 3 and Pin 6, respectively.
2) Connect variable voltage
V0L(1) 3 ' 6 source to Pin 2 and Pin 5. - 0.3 0.5
3) Change variable voltage
source and measure voltages
Low Level V3 and V6 when low.
1) Measure Voltage V4 of Pin 4.
2) Connect variable voltage
source to Pin 1.
VOL(2) 4 3) Change variable voltage - 0.3 0.5
source and measure voltage
V4 when low.
2.5 4.0 -
Input High Level VIH 7,
Voltage Low Level VIL 7
Connect an ammeter to Pin 7
Input High Level and Pin 8. le =4.ov.
Current Connect an ammeter to Pin 7
L L I I 7 . - - A
ow eve Il.. ,8 and Pin 8. 1hL=0.3V. 0 /2
6 2001-06-25
TOSHIBA TA8667P/F
TEST TEST CONDITION
CHARACTERISTIC SYMBOL PIN (SEE "TEST CIRCUIT") MIN. TYP. MAX. UNIT
1) Measure Voltage V4 (V3) of
Pin 4 (Pin 3).
2) Connect variable voltage
source to Pin 1 (Pin 2) through
s nc Se arator In ut an ammeter.
Sinsitivirty Currentp IINS 1,2 3) Change variable voltage - 23 - pA
source and measure the
current outflowed from Pin 1
(Pin 2) on the high to low
transition of V4 (V3).
1) SW1 : Off, SW2 : On 28.6
2) Measure the level of TP1 with - (Note -
counter.
. . f 1 MHz
Oscillating Frequency o 3 3) Adjust the value of the 32.0
variable coil until it reaches - (Note -
15.73kHzXN. 2)
Measure the level of TP1 at the
. . 4. V -
Output Level Vo 13 time when to is measured. 2 0 3 2 0 p p
1) Switch on SW1 in the same
condition that to is measured.
. 2) Input the sync signal of
- - ns
Output Jitter TG 13 15.73kHz to Pin 2. 14
3) Measure the output waveform
of the frequency divider.
(Note 1) VCO TANC : TRF3518D used
(Note 2) VCO TANC : TRF3503K used
7 2001-06-25
TOSHIBA
TA8667P/F
CHARACTERISTIC
SYMBOL
TEST CONDITION
(SEE "TEST CIRCUIT")
Horizontal Frequency
Phase Comparison
Range2
Horizontal Frequency
Hold Range
1) SW1 : Off, SW2 : On.
Pin 2 : Open.
2) Measure the frequency of
3) Adjust the value of the
variable coil until it reaches
15.73kHZxN (fo=32.2MHz).
4) SW1 : On
5) Connect S.G* to Pin 2.
6) Measure the power supply of
7) Raise the S.G* frequency
starting from around 13.6kHz
and measure the frequency
when PLL is locked.
8) Raise the S.G* frequency
further and measure it when
PLL is unlocked.
9) Lower the frequency and
measure it when PLL is locked
again.
10)Lower the frequency further
and measure it when PLL is
unlocked again (See Figure 1).
C.S. OUT Delay Time
(See Figure 2)
Pin2 I I I I I I
5.0V ..
63.5 S .'.'
F-t''us-oi tcsd -.r-
mnrLl'-Ll'- "Y-cy'"-
H. ref IN - C.S. OUT
Steady-State Phase
Difference
(See Figure 3)
1) Switch on SW1 in the same
condition that to is measured.
2) Adjust the value of the
variable coil until it reaches
15.73kHzxN (fo=32.2MHz).
3) Input the sync signal of
15.73kHz to Pin 2.
4) Measure the signal waveforms
of Pin 3 and Pin 7
simultaneously.
* : S.G=Sync Generator
TOSHIBA TA8667P/F
Figure 1
15.7_3kHz
Figure 2
C.S. OUT Delay Time : tcsd
Video IN
c.s. OUT I I I
tcsd I
Figure 3
H. ref IN - CS. OUT Steady-State Phase Difference : tafce
I I T/2 T/2
C.S. OUT I l I I l
t I - I - T
, - I l—
H. ref IN I I
_.I u- = 'u-
tafce tafce
9 2001-06-25
TOSHIBA TA8667P/F
TEST CIRCUIT (Pin assignment for TA8667P)
a m 11
SW1 :4; :1; I f;
o\c OTP1 rn' + S
LL LL ci
g I 3 2SC 8 ti,r,x"
'R 1 15 .
var/tble-cy :3 + Io . - OTP2 Icfsw
I I SW2
I-----' F-o
18 17 16 15 14 13 12 GD 10
. TA8667P
TTTETTWL
Variable coil (VCO TANK) : Select an inductance suited for the oscillating frequency.
PRECAUTIONS
V. Mask IN (See Figure 4, "An example of V. Mask IN timing")
Driving the V. Mask IN signal to high stops phase-comparison operation.
Adjust the signal so that equalizing pulse of video signal and vertical sync signal are masked.
Masking some parts of horizontal sync signal and video signal do not cause a problem.
However, the rise and fall of V. Mask IN must not occur while horizontal sync signal and
equalizing pulse are low - the time indicated with " l " in Figure 4, for example.
Figure 4 "An example of V. Mask IN timing"
cEqualizing pulse, Vertical sync signal Equalizing pulse
VideolN i:lr,j-r.:r.ri.irr,.i-..ri..i 11 1_ 1
cEqualizing pulse, Vertical sync signal Equalizing pulse
l l P T T l 4 l
(rjlj7rLfulJL0 In - l)
F Maskingtime =l - VIH
V. Mask IN
10 2001-06-25
TOSHIBA TA8667P/F
CD Example of VCO TANK Specification for 32MHz clock (TRF3503K)
When f=7.96MHz :
{L=2.35,uH (Varied within more than ur15%)
C) Example of VCO TANK Specification for 28MHz clock (TRF3518D)
When f=7.96MHz :
(ree" (Varied within more than i15%)
SAMPLE APPLICATION 1 (Pin Assignment for TA8667P)
An example of 28.6MH2 clock generation. 5.1kQ 0.47PF
TRF3518D used. Cl w. +g - cl
- i ILL jiid:
o u, '" l cu
c.s. OUT o, v. OUT
3 v. Sepa OUTQ C) 5 v. IN G)
v. Sepa IN -ICj) Vcc1
Video In 3300 0-471”
+ - - v. Sync Ch, - 5mm;
(ZVp.p) l j"
'e ' . -D Vcc2
H.V. Sepa IN
1600 2000 Wave
- H.V. Sync Phase Comp. VCO Cont. - VCO - -
'k shaping 28.6MHZ
I', f- --_--_- J
i -D GND1
V. Mask ------ -'
His) GND2
P.D. ou
v. Mask IN (if) H. ref IN p
u. 8 VCO TANK
:5 E (TRF3518D)
15.7kHz 1 28.6MH2
The above illustration shows an example for application and may require modification in
constant and circuit for practical design.
11 2001-06-25
TOSHIBA TA8667P/F
PACKAGE DIMENSIONS
DIP18-P-300-2.54D Unit : mm
18 10 fi,
J-ll-ll-lr-nr-ll-Ir-Ir-nr-n d qi''''
p) a tl,
mt. ts
't 25.1MAX
24.6:t0.2 _
4.1 510.;
2.14TYP
Weight : 1.47g (Typ.)
12 2001-06-25
TOSHIBA TA8667P/F
PACKAGE DIMENSIONS
SSOP24-P-300-1.00B Unit : mm
f4FlFlFlFlFlFlFIRRFlFi " "
6 OiO 2
8.0i0.3
Q ,' I l
'tllelglt'lldgldldlelglejld_.....,._,, =
1 l 12
1.0TYP 0.4d:0.1 Eamwl
v, 13.5MAX rd
a 13.0:02 .el
cu. A (g
33...; e?
1rccaatssssscarl'] It? os. “’
N"'" ,. 1"
---2--ir- o
V015 *3
Weight : 0.32g (Typ.)
13 2001-06-25
TOSHIBA TA8667P/F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
14 2001-06-25
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